[Intel-gfx] [PATCH] drm/i915/hsw: Change default LLC age to 3

[Chad Versace]

On 07/31/2013 04:07 PM, Ben Widawsky wrote:
> The default LLC age was changed:
> commit 0d8ff15e9a15f2b393e53337a107b7a1e5919b6d
> Author: Ben Widawsky <benjamin.widawsky at intel.com>
> Date:   Thu Jul 4 11:02:03 2013 -0700
>
> drm/i915/hsw: Set correct Haswell PTE encodings.
>
> This caused a regression in performance on certain benchmarks. While I
> think a discussion still needs to happen about how the kernel should
> default for both eLLC, and LLC - just revert this behavior for now.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=67062
> Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
> ---
>   drivers/gpu/drm/i915/i915_gem_gtt.c | 4 +++-
>   1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index e7b4204..4b1e6e3 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -52,8 +52,10 @@
>    */
>   #define HSW_CACHEABILITY_CONTROL(bits)	((((bits) & 0x7) << 1) | \
>   					 (((bits) & 0x8) << (11 - 3)))
> +#define HSW_WB_LLC_AGE3			HSW_CACHEABILITY_CONTROL(0x2)
>   #define HSW_WB_LLC_AGE0			HSW_CACHEABILITY_CONTROL(0x3)
>   #define HSW_WB_ELLC_LLC_AGE0		HSW_CACHEABILITY_CONTROL(0xb)
> +#define HSW_LLC				HSW_WB_LLC_AGE3
>
>   static gen6_gtt_pte_t gen6_pte_encode(dma_addr_t addr,
>   				      enum i915_cache_level level)
> @@ -105,7 +107,7 @@ static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr,
>   	pte |= HSW_PTE_ADDR_ENCODE(addr);
>
>   	if (level != I915_CACHE_NONE)
> -		pte |= HSW_WB_LLC_AGE0;
> +		pte |= HSW_LLC;
>
>   	return pte;
>   }
>

I think the patch is clearer without the wrapper define HSW_LLC. But,
anyways, with or without the wrapper,
Reviewed-by: Chad Versace <chad.versace at linux.intel.com>