[Intel-gfx] [PATCH v2 14/17] drm/i915: Print the watermark latencies during init

[Ville Syrjälä]

On Fri, Aug 02, 2013 at 11:41:31AM -0300, Paulo Zanoni wrote:
> 2013/8/1  <ville.syrjala at linux.intel.com>:
> > From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> >
> > Seeing the watermark latency values in dmesg might help sometimes.
> >
> > v2: Use DRM_ERROR() when expected latency values are missing
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 37 +++++++++++++++++++++++++++++++++++++
> >  1 file changed, 37 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index f754ca2..53967ef 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -2394,6 +2394,39 @@ static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
> >                 wm[3] *= 2;
> >  }
> >
> > +static void intel_print_wm_latency(struct drm_device *dev,
> > +                                  const char *name,
> > +                                  const uint16_t wm[5])
> > +{
> > +       int level, max_level;
> > +
> > +       /* how many WM levels are we expecting */
> > +       if (IS_HASWELL(dev))
> > +               max_level = 4;
> > +       else if (INTEL_INFO(dev)->gen >= 6)
> > +               max_level = 3;
> > +       else
> > +               max_level = 2;
> > +
> > +       for (level = 0; level <= max_level; level++) {
> > +               unsigned int latency = wm[level];
> > +
> > +               if (latency == 0) {
> > +                       DRM_ERROR("%s WM%d latency not provided\n",
> > +                                 name, level);
> 
> On your last email you mentioned that we may start getting bug reports
> that we can't do anything about. You're right, I guess if we start
> getting these reports we should probably tune the message to
> DRM_DEBUG_KMS then.

Yeah. Another idea that I had is that we could store the max WM
level into dev_priv based on which levels have non-zero latencies.
That way we'd avoid ever hitting the case where we try to compute
a watermark w/ latency==0. But I didn't implement this yet.

> 
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
> 
> > +                       continue;
> > +               }
> > +
> > +               /* WM1+ latency values in 0.5us units */
> > +               if (level > 0)
> > +                       latency *= 5;
> > +
> > +               DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
> > +                             name, level, wm[level],
> > +                             latency / 10, latency % 10);
> > +       }
> > +}
> > +
> >  static void intel_setup_wm_latency(struct drm_device *dev)
> >  {
> >         struct drm_i915_private *dev_priv = dev->dev_private;
> > @@ -2407,6 +2440,10 @@ static void intel_setup_wm_latency(struct drm_device *dev)
> >
> >         intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
> >         intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
> > +
> > +       intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
> > +       intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
> > +       intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
> >  }
> >
> >  static void hsw_compute_wm_parameters(struct drm_device *dev,
> > --
> > 1.8.1.5
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx at lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> 
> 
> -- 
> Paulo Zanoni

-- 
Ville Syrjälä
Intel OTC