[Intel-gfx] [PATCH 1/4] drm/i915: Rename I915_CACHE_MLC_LLC to L3_LLC for Ivybridge
Daniel Vetter
daniel at ffwll.ch
Tue Aug 6 16:36:20 CEST 2013
On Tue, Aug 06, 2013 at 05:25:22PM +0300, Ville Syrjälä wrote:
> On Tue, Aug 06, 2013 at 01:17:02PM +0100, Chris Wilson wrote:
> > MLC_LLC was never validated for Sandybridge and was superseded by a new
> > level of cacheing for the GPU in Ivybridge. Update our names to be
> > consistent with usage, and in the process stop setting the unwanted bit
> > on Sandybridge.
> >
> > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 7 +++++--
> > drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
> > drivers/gpu/drm/i915/i915_gem_gtt.c | 35 +++++++++++++++++++++++++++------
> > drivers/gpu/drm/i915/i915_gpu_error.c | 4 ++--
> > 4 files changed, 37 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index cb2c59d..aa11731 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -450,8 +450,11 @@ struct intel_device_info {
> >
> > enum i915_cache_level {
> > I915_CACHE_NONE = 0,
> > - I915_CACHE_LLC,
> > - I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */
> > + I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
> > + I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
> > + caches, eg sampler/render caches, and the
> > + large Last-Level-Cache. LLC is coherent with
> > + the CPU, but L3 is only visible to the GPU. */
> > };
> >
> > typedef uint32_t gen6_gtt_pte_t;
> > diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> > index 30bb01a..db94aca 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_context.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> > @@ -158,7 +158,7 @@ create_hw_context(struct drm_device *dev,
> >
> > if (INTEL_INFO(dev)->gen >= 7) {
> > ret = i915_gem_object_set_cache_level(ctx->obj,
> > - I915_CACHE_LLC_MLC);
> > + I915_CACHE_L3_LLC);
> > /* Failure shouldn't ever happen this early */
> > if (WARN_ON(ret))
> > goto err_out;
> > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > index 3d779cd..06f4eb3 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > @@ -43,7 +43,7 @@
> > #define GEN6_PTE_UNCACHED (1 << 1)
> > #define HSW_PTE_UNCACHED (0)
> > #define GEN6_PTE_CACHE_LLC (2 << 1)
> > -#define GEN6_PTE_CACHE_LLC_MLC (3 << 1)
> > +#define GEN7_PTE_CACHE_L3_LLC (3 << 1)
>
> BSpec is quite confused about these bits (PPGTT text says one thing,
> GGTT text seems to have been copied from MOCS text, MOCS matches PTE
> for SNB, not for IVB, etc.). But unless we find someone who can tell
> us more, or we come up with some test to really verify this stuff I
> think it's as good as it gets.
>
> So,
> Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
Queued for -next (with a tiny s/BUG/WARN_ON/ bikeshed applied), thanks for
the patch.
-Daniel
>
> > #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
> > #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr)
> >
> > @@ -56,15 +56,36 @@
> > #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3)
> > #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb)
> >
> > -static gen6_gtt_pte_t gen6_pte_encode(dma_addr_t addr,
> > - enum i915_cache_level level)
> > +static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr,
> > + enum i915_cache_level level)
> > +{
> > + gen6_gtt_pte_t pte = GEN6_PTE_VALID;
> > + pte |= GEN6_PTE_ADDR_ENCODE(addr);
> > +
> > + switch (level) {
> > + case I915_CACHE_L3_LLC:
> > + case I915_CACHE_LLC:
> > + pte |= GEN6_PTE_CACHE_LLC;
> > + break;
> > + case I915_CACHE_NONE:
> > + pte |= GEN6_PTE_UNCACHED;
> > + break;
> > + default:
> > + BUG();
> > + }
> > +
> > + return pte;
> > +}
> > +
> > +static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr,
> > + enum i915_cache_level level)
> > {
> > gen6_gtt_pte_t pte = GEN6_PTE_VALID;
> > pte |= GEN6_PTE_ADDR_ENCODE(addr);
> >
> > switch (level) {
> > - case I915_CACHE_LLC_MLC:
> > - pte |= GEN6_PTE_CACHE_LLC_MLC;
> > + case I915_CACHE_L3_LLC:
> > + pte |= GEN7_PTE_CACHE_L3_LLC;
> > break;
> > case I915_CACHE_LLC:
> > pte |= GEN6_PTE_CACHE_LLC;
> > @@ -880,8 +901,10 @@ int i915_gem_gtt_init(struct drm_device *dev)
> > gtt->base.pte_encode = hsw_pte_encode;
> > else if (IS_VALLEYVIEW(dev))
> > gtt->base.pte_encode = byt_pte_encode;
> > + else if (INTEL_INFO(dev)->gen >= 7)
> > + gtt->base.pte_encode = ivb_pte_encode;
> > else
> > - gtt->base.pte_encode = gen6_pte_encode;
> > + gtt->base.pte_encode = snb_pte_encode;
> > }
> >
> > ret = gtt->gtt_probe(dev, >t->base.total,
> > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> > index d970d84..8091485 100644
> > --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> > @@ -938,8 +938,8 @@ const char *i915_cache_level_str(int type)
> > {
> > switch (type) {
> > case I915_CACHE_NONE: return " uncached";
> > - case I915_CACHE_LLC: return " snooped (LLC)";
> > - case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)";
> > + case I915_CACHE_LLC: return " snooped or LLC";
> > + case I915_CACHE_L3_LLC: return " L3+LLC";
> > default: return "";
> > }
> > }
> > --
> > 1.8.4.rc1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx at lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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