[Intel-gfx] [PATCH 9/9] drm/i915: Allow the user to set bo into the DISPLAY cache domain

[Chris Wilson]

On Sat, Aug 10, 2013 at 12:09:26PM +0200, Daniel Vetter wrote:
> On Thu, Aug 08, 2013 at 02:41:11PM +0100, Chris Wilson wrote:
> > This is primarily for the benefit of the create2 ioctl so that the
> > caller can avoid the later step of rebinding the bo with new PTE bits.
> > After introducing WT (and possibly GFDT) cacheing for display targets,
> > not everything in the display is earmarked as UC, and more importantly
> > what is is controlled by the kernel.
> > 
> > Note that set_cache_level/get_cache_level for DISPLAY is not necessarily
> > idempotent; get_cache_level may return UC for architectures that have no
> > special cache domain for the display engine.
> > 
> > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> 
> You know the drill: A bit of igt testcoverage would be neat, I think
> simply adding the display domain everywhere we test uncached/snooped
> already should be more than good enough. So I'll punt on this one here for
> now, all other patches (with the exception of the hw context from stolen
> one) are merged to dinq.

Catch-22, you will not get igt until you at least reserve the enum.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre