[Intel-gfx] [PATCH] CHROMIUM: drm/i915: Improve RC6p stability

[james.ausmus at intel.com]

From: Stéphane Marchesin <marcheu at chromium.org>

When the CPU is loaded and the GPU tries to switch RC6p modes, the GPU
sometimes gets stuck in RC6p mode and doesn't come out of it. I suspect
that our voltage rail is too weak and sometimes falls behind.

This change throttles down the number of RC6p transitions we do to appease it.

The change also disables clock gating which seems to help. Upstream commit
which does that is 0f846f81a154cc1818416918d22939bda73da194
(drm/i915: disable RCBP and VDS unit clock gating on SNB and VL)

I tested this on multiple Link machines for hours. The number of RC6 problems
went down from ~ one every 15 minutes to ~ one every 25 hours. So this is not
a complete solution, but I suspect there might be another, more difficult to
reproduce, problem. In any case it reduces the issue significantly, to the
point where we might be able to forget about it.

I measured the power usage on idle before/after this patch and saw no
difference. Obviously when the GPU load varies, it will consume more power
since it now takes more time to adapt.

Also note that not all machines seem to react equally. Some crash fairly
often, and some less often. So this will improve the situation to different
extents for different people.

BUG=chrome-os-partner:16886,chrome-os-partner:11474
TEST=ran the factory stress test (RunIn.Stress) on multiple Link machines for
TEST=about 100 hours, saw only 4 RC6 crashes.

Change-Id: I1135d90e2a155424388d23c6e0879a210b4a0146
[sonnyrao: 3.8: parts upstream, move RC6p_THRESHOLD change to intel_pm.c]
Reviewed-on: https://gerrit.chromium.org/gerrit/42084
Tested-by: Stéphane Marchesin <marcheu at chromium.org>
Reviewed-by: Vincent Palatin <vpalatin at chromium.org>
Reviewed-by: Sameer Nanda <snanda at chromium.org>
Commit-Queue: Stéphane Marchesin <marcheu at chromium.org>
---
 drivers/gpu/drm/i915/intel_pm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7e1c629..c86f432 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2573,7 +2573,7 @@ static void gen6_enable_rps(struct drm_device *dev)
 	I915_WRITE(GEN6_RC_SLEEP, 0);
 	I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
 	I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
-	I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
+	I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
 	I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
 
 	/* Check if we are enabling RC6 */
-- 
1.8.3.2