[Intel-gfx] [PATCH] CHROMIUM: drm/i915: Don't load boot context at init time on SNB

[james.ausmus at intel.com]

From: Stéphane Marchesin <marcheu at chromium.org>

This breaks video decode on SNB, so let's not do it.

BUG=chromium:260836
TEST=by hand, video works after resume

Change-Id: I059b022ba1379599f219ad0828e3b4d0e0195f0b
Reviewed-on: https://gerrit.chromium.org/gerrit/65431
Tested-by: Stéphane Marchesin <marcheu at chromium.org>
Reviewed-by: Ilja H. Friedel <ihf at chromium.org>
Commit-Queue: Stéphane Marchesin <marcheu at chromium.org>
Reviewed-by: Antoine Labour <piman at chromium.org>
---
 drivers/gpu/drm/i915/intel_pm.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 73f35cb..4d63d53 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4268,8 +4268,9 @@ static void gen6_init_clock_gating(struct drm_device *dev)
 		   ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
 
 	/* WaMbcDriverBootEnable */
-	I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
-		   GEN6_MBCTL_ENABLE_BOOT_FETCH);
+	/* This breaks video on resume */
+/*	I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
+		   GEN6_MBCTL_ENABLE_BOOT_FETCH);*/
 
 	for_each_pipe(pipe) {
 		I915_WRITE(DSPCNTR(pipe),
-- 
1.8.3.2