[Intel-gfx] [PATCH 3/6] drm/i915: allow package C8+ states on Haswell (disabled)

[Chris Wilson]

On Mon, Aug 19, 2013 at 01:18:09PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni at intel.com>
> 
> This patch allows PC8+ states on Haswell. These states can only be
> reached when all the display outputs are disabled, and they allow some
> more power savings.
> 
> The fact that the graphics device is allowing PC8+ doesn't mean that
> the machine will actually enter PC8+: all the other devices also need
> to allow PC8+.
> 
> For now this option is disabled by default. You need i915.allow_pc8=1
> if you want it.
> 
> This patch adds a big comment inside i915_drv.h explaining how it
> works and how it tracks things. Read it.
> 
> v2: (this is not really v2, many previous versions were already sent,
>      but they had different names)
>     - Use the new functions to enable/disable GTIMR and GEN6_PMIMR
>     - Rename almost all variables and functions to names suggested by
>       Chris
>     - More WARNs on the IRQ handling code
>     - Also disable PC8 when there's GPU work to do (thanks to Ben for
>       the help on this), so apps can run caster
>     - Enable PC8 on a delayed work function that is delayed for 5
>       seconds. This makes sure we only enable PC8+ if we're really
>       idle
>     - Make sure we're not in PC8+ when suspending
> v3: - WARN if IRQs are disabled on __wait_seqno
>     - Replace some DRM_ERRORs with WARNs
>     - Fix calls to restore GT and PM interrupts
>     - Use intel_mark_busy instead of intel_ring_advance to disable PC8
> v4: - Use the force_wake, Luke!
> v5: - Remove the "IIR is not zero" WARNs
>     - Move the force_wake chunk to its own patch
>     - Only restore what's missing from RC6, not everything
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>

I think this is a nice looking patch now, and I think I understand what
you need from this patch alone, so
Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre