[Intel-gfx] [PATCH v2 03/15] drm/i915: add VLV pipeconf bit definition for DSI PLL lock

[Ville Syrjälä]

On Fri, Aug 16, 2013 at 03:35:51PM +0300, Jani Nikula wrote:
> Signed-off-by: Jani Nikula <jani.nikula at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |    1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b417a8c..2f8e341 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2972,6 +2972,7 @@
>  #define   PIPECONF_DISABLE	0
>  #define   PIPECONF_DOUBLE_WIDE	(1<<30)
>  #define   I965_PIPECONF_ACTIVE	(1<<30)
> +#define   PIPECONF_DSI_PLL_LOCKED	(1<<29) /* vlv only */

Maybe add a comment that it's only in the pipe A register
(at least according to spec).

>  #define   PIPECONF_FRAME_START_DELAY_MASK (3<<27)
>  #define   PIPECONF_SINGLE_WIDE	0
>  #define   PIPECONF_PIPE_UNLOCKED 0
> -- 
> 1.7.9.5
> 
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-- 
Ville Syrjälä
Intel OTC