[Intel-gfx] [PATCH] RFC drm/i915: Expose a PMU interface for perf queries

Daniel Vetter daniel at ffwll.ch
Wed Aug 21 15:14:22 CEST 2013


On Tue, Aug 20, 2013 at 10:17 PM, Chris Wilson <chris at chris-wilson.co.uk> wrote:
> The first goal is to be able to measure GPU (and invidual ring) busyness
> without having to poll registers from userspace. (Which not only incurs
> holding the forcewake lock indefinitely, perturbing the system, but also
> runs the risk of hanging the machine.) As an alternative we can use the
> perf event counter interface to sample the ring registers periodically
> and send those results to userspace.
>
> To be able to do so, we need to export the two symbols from
> kernel/events/core.c to register and unregister a PMU device.
>
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>

Make sense imo to move the perf gathering into the kernel, a few
random (and rather uninformed) points I've thought of:
- What about the instdone busy bits intel_gpu_top currently presents?
- Shouldn't we have one polling hrtimer that checks all enabled pmu event bits?
- Plans for integrating the various status/debug bits in the display
block (like fetches, fbc compression stuff, ...)? I know that this
will tickle the all-encompassing paranoia about releasing performance
counter details, but we can still hope. Iirc there's also some very
minimal perf counter stuff on the GT arbiter.

Overall I think this is great and should fill the gap until we're
allowed to release some more of the integrated global perf counters
(and even then those should neatly fit in ...).

For testing I think just running your overlay tool with all possible
events should be good enough (in some headless mode ofc) - functional
testing of perf counter is imo too much fuss.

Cheers, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch



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