[Intel-gfx] [PATCH 3/3] RFM drm/i915: Tweak RPS thresholds to more aggressively downclock

[Chris Wilson]

After applying wait-boost we often find ourselves stuck at higher clocks
than required. The current threshold value requires the GPU to be
continuously and completely idle for 313ms before it is dropped by one
bin. Conversely, we require the GPU to be busy for an average of 90% over
a 84ms before we upclock. So the current thresholds almost never
downclock the GPU, and respond very slowly to sudden demands for more
power.

A more sensible approach, as discussed in the bspec, is to a continuous
threshold for upclocking, and an average value for downclocking.

RFM - request for measurement!

Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth at whitecape.org>
Cc: Stéphane Marchesin <stephane.marchesin at gmail.com>
Cc: "Meng, Mengmeng" <mengmeng.meng at intel.com>
Cc: "Zhuang, Lena" <lena.zhuang at intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |  2 +-
 drivers/gpu/drm/i915/intel_pm.c | 15 +++++++++------
 2 files changed, 10 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3f5bddd..04b23cb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4620,7 +4620,7 @@
 #define   GEN6_RP_UP_IDLE_MIN			(0x1<<3)
 #define   GEN6_RP_UP_BUSY_AVG			(0x2<<3)
 #define   GEN6_RP_UP_BUSY_CONT			(0x4<<3)
-#define   GEN7_RP_DOWN_IDLE_AVG			(0x2<<0)
+#define   GEN6_RP_DOWN_IDLE_AVG			(0x2<<0)
 #define   GEN6_RP_DOWN_IDLE_CONT		(0x1<<0)
 #define GEN6_RP_UP_THRESHOLD			0xA02C
 #define GEN6_RP_DOWN_THRESHOLD			0xA030
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index aa98b0b..1dcda84 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3581,10 +3581,13 @@ static void gen6_enable_rps(struct drm_device *dev)
 		   dev_priv->rps.max_delay << 24 |
 		   dev_priv->rps.min_delay << 16);
 
-	I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
-	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
-	I915_WRITE(GEN6_RP_UP_EI, 66000);
-	I915_WRITE(GEN6_RP_DOWN_EI, 350000);
+	/* Upclock if continuously busy for 5ms, ~1/3 of a frame */
+	I915_WRITE(GEN6_RP_UP_EI, 16000); /* not used for continuous mode */
+	I915_WRITE(GEN6_RP_UP_THRESHOLD, 5000);
+
+	/* Downclock if less than 66% busy over 33ms, last ~2 frames */
+	I915_WRITE(GEN6_RP_DOWN_EI, 33000);
+	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 22000);
 
 	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
 	I915_WRITE(GEN6_RP_CONTROL,
@@ -3592,8 +3595,8 @@ static void gen6_enable_rps(struct drm_device *dev)
 		   GEN6_RP_MEDIA_HW_NORMAL_MODE |
 		   GEN6_RP_MEDIA_IS_GFX |
 		   GEN6_RP_ENABLE |
-		   GEN6_RP_UP_BUSY_AVG |
-		   (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
+		   GEN6_RP_UP_BUSY_CONT |
+		   GEN6_RP_DOWN_IDLE_AVG);
 
 	ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
 	if (!ret) {
-- 
1.8.4.rc3