[Intel-gfx] [PATCH 6/6] DRAFT: drm/i915: do adapter power state notification on PC8+ enable/disable

[Paulo Zanoni]

2013/8/30 Jani Nikula <jani.nikula at intel.com>:
> v2:
>  - go to PCI_D3cold
>  - shuffle the call site a bit

Ok, so I know I'm the one who requested to shuffle the call site, but
it's because I thought that when we disable LCPLL we actually put the
device in D3. After some experimentation last week, we discovered we
need to write a PCI config register to actually enable D3, so your
call to intel_opregion_notify_adapter should probably be glued to that
write (which we don't have yet). The problem is that if we really put
the device in D3, all the registers go away, so we need to properly
recover from that. I think it makes sense to postpone this patch until
we have the actual code to put our device in D3 and properly restore
from it. So my suggestion is to merge patches 1-5 so we can work on
the D3 feature on top of the work you already completed.

Thanks,
Paulo

>
> Signed-off-by: Jani Nikula <jani.nikula at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c |    2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 83d853f..e33fa6d 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6126,6 +6126,7 @@ void hsw_enable_pc8_work(struct work_struct *__work)
>
>         lpt_disable_clkout_dp(dev);
>         hsw_pc8_disable_interrupts(dev);
> +       intel_opregion_notify_adapter(dev, PCI_D3cold);
>         hsw_disable_lcpll(dev_priv, true, true);
>  }
>
> @@ -6163,6 +6164,7 @@ static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
>         DRM_DEBUG_KMS("Disabling package C8+\n");
>
>         hsw_restore_lcpll(dev_priv);
> +       intel_opregion_notify_adapter(dev, PCI_D0);
>         hsw_pc8_restore_interrupts(dev);
>         lpt_init_pch_refclk(dev);
>
> --
> 1.7.10.4
>



-- 
Paulo Zanoni