[Intel-gfx] [PATCH 04/19] drm/i915: Use ilk_compute_wm_level to compute WM_PIPE values

[Paulo Zanoni]

2013/8/30  <ville.syrjala at linux.intel.com>:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> Unify the code a bit to use ilk_compute_wm_level for all watermark
> levels.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

Looks correct and doesn't change the WM values set on my specific
eDP+HDMI config here...

Reviewed-by: Paulo Zanoni <paulo.r.zanoni at intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 44 ++++++++++++++++++++---------------------
>  1 file changed, 21 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 96493dc..d118ee1 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2460,33 +2460,31 @@ static bool hsw_compute_lp_wm(struct drm_i915_private *dev_priv,
>         return ilk_check_wm(level, max, result);
>  }
>
> -static uint32_t hsw_compute_wm_pipe(struct drm_i915_private *dev_priv,
> -                                   enum pipe pipe,
> +
> +static uint32_t hsw_compute_wm_pipe(struct drm_device *dev,
>                                     const struct hsw_pipe_wm_parameters *params)
>  {
> -       uint32_t pri_val, cur_val, spr_val;
> -       /* WM0 latency values stored in 0.1us units */
> -       uint16_t pri_latency = dev_priv->wm.pri_latency[0];
> -       uint16_t spr_latency = dev_priv->wm.spr_latency[0];
> -       uint16_t cur_latency = dev_priv->wm.cur_latency[0];
> +       struct drm_i915_private *dev_priv = dev->dev_private;
> +       struct intel_wm_config config = {
> +               .num_pipes_active = 1,
> +               .sprites_enabled = params->spr.enabled,
> +               .sprites_scaled = params->spr.scaled,
> +       };
> +       struct hsw_wm_maximums max;
> +       struct intel_wm_level res;
> +
> +       if (!params->active)
> +               return 0;
> +
> +       ilk_wm_max(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
>
> -       pri_val = ilk_compute_pri_wm(params, pri_latency, false);
> -       spr_val = ilk_compute_spr_wm(params, spr_latency);
> -       cur_val = ilk_compute_cur_wm(params, cur_latency);
> +       ilk_compute_wm_level(dev_priv, 0, params, &res);
>
> -       WARN(pri_val > 127,
> -            "Primary WM error, mode not supported for pipe %c\n",
> -            pipe_name(pipe));
> -       WARN(spr_val > 127,
> -            "Sprite WM error, mode not supported for pipe %c\n",
> -            pipe_name(pipe));
> -       WARN(cur_val > 63,
> -            "Cursor WM error, mode not supported for pipe %c\n",
> -            pipe_name(pipe));
> +       ilk_check_wm(0, &max, &res);
>
> -       return (pri_val << WM0_PIPE_PLANE_SHIFT) |
> -              (spr_val << WM0_PIPE_SPRITE_SHIFT) |
> -              cur_val;
> +       return (res.pri_val << WM0_PIPE_PLANE_SHIFT) |
> +              (res.spr_val << WM0_PIPE_SPRITE_SHIFT) |
> +              res.cur_val;
>  }
>
>  static uint32_t
> @@ -2715,7 +2713,7 @@ static void hsw_compute_wm_results(struct drm_device *dev,
>         }
>
>         for_each_pipe(pipe)
> -               results->wm_pipe[pipe] = hsw_compute_wm_pipe(dev_priv, pipe,
> +               results->wm_pipe[pipe] = hsw_compute_wm_pipe(dev,
>                                                              &params[pipe]);
>
>         for_each_pipe(pipe) {
> --
> 1.8.1.5
>
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-- 
Paulo Zanoni