[Intel-gfx] [PATCH 4/4] drm/i915: Cleanup the DP_AUX_CTL macros

[Damien Lespiau]

Let's use a less verbose version to fill the DP_AUX_CTL register.
Improves the readability a little bit. Also sort the fields by their
place in the register.

Signed-off-by: Damien Lespiau <damien.lespiau at intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |  8 ++++----
 drivers/gpu/drm/i915/intel_dp.c | 18 +++++++++---------
 2 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3be449d..35ae2b3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3105,15 +3105,15 @@
 #define   DP_AUX_CH_CTL_RECEIVE_ERROR	    (1 << 25)
 #define   DP_AUX_CH_CTL_MESSAGE_SIZE_MASK    (0x1f << 20)
 #define   DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT   20
-#define   DP_AUX_CH_CTL_PRECHARGE_2US_MASK   (0xf << 16)
-#define   DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT  16
+#define   DP_AUX_CH_CTL_MESSAGE_SIZE(s) \
+	((s) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT)
+#define   DP_AUX_CH_CTL_PRECHARGE(p)	    ((p) << 16)
 #define   DP_AUX_CH_CTL_AUX_AKSV_SELECT	    (1 << 15)
 #define   DP_AUX_CH_CTL_MANCHESTER_TEST	    (1 << 14)
 #define   DP_AUX_CH_CTL_SYNC_TEST	    (1 << 13)
 #define   DP_AUX_CH_CTL_DEGLITCH_TEST	    (1 << 12)
 #define   DP_AUX_CH_CTL_PRECHARGE_TEST	    (1 << 11)
-#define   DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK    (0x7ff)
-#define   DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT   0
+#define   DP_AUX_CH_CTL_CLOCK_2X(c)	    (c)
 
 /*
  * Computing GMCH M and N values for the Display Port link
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 07fcc9e..a1113af 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -454,14 +454,14 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
 			/* Send the command and wait for it to complete */
 			I915_WRITE(ch_ctl,
 				   DP_AUX_CH_CTL_SEND_BUSY |
-				   DP_AUX_CH_CTL_INTERRUPT |
-				   timeout |
-				   (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
-				   (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
-				   (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 				   DP_AUX_CH_CTL_DONE |
+				   DP_AUX_CH_CTL_INTERRUPT |
 				   DP_AUX_CH_CTL_TIME_OUT_ERROR |
-				   DP_AUX_CH_CTL_RECEIVE_ERROR);
+				   timeout |
+				   DP_AUX_CH_CTL_RECEIVE_ERROR |
+				   DP_AUX_CH_CTL_MESSAGE_SIZE(send_bytes) |
+				   DP_AUX_CH_CTL_PRECHARGE(precharge) |
+				   DP_AUX_CH_CTL_CLOCK_2X(aux_clock_divider));
 
 			status = intel_dp_aux_wait_done(intel_dp);
 
@@ -1599,9 +1599,9 @@ static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
 	I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
 	I915_WRITE(EDP_PSR_AUX_CTL(dev),
 		   DP_AUX_CH_CTL_TIME_OUT_400us |
-		   (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
-		   (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
-		   (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
+		   DP_AUX_CH_CTL_MESSAGE_SIZE(msg_size) |
+		   DP_AUX_CH_CTL_PRECHARGE(precharge) |
+		   DP_AUX_CH_CTL_CLOCK_2X(aux_clock_divider));
 }
 
 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
-- 
1.8.3.1