[Intel-gfx] [PATCH 4/4] drm/i915: WA to fix Voltage is not getting dropped to Vmin when Gfx is power gated.
Daniel Vetter
daniel at ffwll.ch
Mon Dec 9 09:35:46 CET 2013
On Sun, Dec 08, 2013 at 02:16:46PM +0530, deepak.s at intel.com wrote:
> From: Deepak S <deepak.s at intel.com>
>
> Voltage is not getting dropped to Vmin when GFX enters RC6 and running
> in/out of turbo frequency. When we enter RC6 and GFX Clocks are off, the
> voltage remains higher than Vmin. As GFX does not request lower
> frequencies when it is power gated. Ideally the Voltage should be
> dropped to Vmin, To fix this we check for Gfx Idle, and set the freq to
> RPe.
>
> Signed-off-by: Deepak S <deepak.s at intel.com>
Do we really still need this patch on upstream?
- It reads the synchronous punit wait loops which we've killed in
commit 4c7915616a7a09be0c1e5b76c26381df15fe671b
Author: Ville Syrjälä <ville.syrjala at linux.intel.com>
Date: Thu Nov 7 19:57:48 2013 +0200
drm/i915: Kill vlv_update_rps_cur_delay()
- It seems to only set the gpu to the lowest freq (RPe which is RPe after
your previous patch), which we already do since Chris sw-controlled
throttle/de-throttle work.
Iirc both of these aren't in the current vlv android tree. If we indeed
need a special dance to whack the gpu into Vmin then I think we need a bit
more comments (and I'd prefer if we have an explicit check for Vmin
instead of going through the rps delay and hoping for the best).
-Daniel
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 +++
> drivers/gpu/drm/i915/intel_pm.c | 78 ++++++++++++++++++++++++++++++++++++++++-
> 2 files changed, 81 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3be449d..e48ed32 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4967,6 +4967,10 @@
> GEN6_PM_RP_DOWN_THRESHOLD | \
> GEN6_PM_RP_DOWN_TIMEOUT)
>
> +#define VLV_GTLC_SURVIVABILITY_REG 0x130098
> +#define VLV_GFX_CLK_STATUS_BIT (1<<3)
> +#define VLV_GFX_CLK_FORCE_ON_BIT (1<<2)
> +
> #define GEN6_GT_GFX_RC6_LOCKED 0x138104
> #define VLV_COUNTER_CONTROL 0x138104
> #define VLV_COUNT_RANGE_HIGH (1<<15)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 6b80ec4..347d77b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3581,12 +3581,87 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
> trace_intel_gpu_freq_change(val * 50);
> }
>
> +/* vlv_set_rps_idle: Set the frequency to Rpe if Gfx clocks are down
> + *
> + * If Gfx clock is UP, then reset the timer as there is a possibility
> + * that normal Turbo logic can bring down the freq to Rpe.
> + * If Gfx clock is Down, then
> + * 1. Mask Turbo interrupts
> + * 2. Bring up Gfx clock
> + * 3. Change the freq to Rpe and wait till P-Unit updates freq
> + * 4. Clear the Force GFX CLK ON bit so that Gfx can down
> + * 5. Unmask Turbo interrupts
> +*/
> +static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
> +{
> +
> + /*
> + * When we are idle. Drop to min voltage state.
> + * Note: we use RPe here since it should match the
> + * Vmin we were shooting for. That should give us better
> + * perf when we come back out of RC6 than if we used the
> + * min freq available.
> + */
> +
> + if (dev_priv->rps.cur_delay <= dev_priv->rps.rpe_delay)
> + return;
> +
> + if (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT) {
> + /* GT is not power gated. Let's wait for normal
> + * Turbo Logic can bring down the freq to RPe.
> + * */
> + vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
> + dev_priv->rps.rpe_delay);
> +
> + /* Make sure Rpe is set by P-Unit*/
> + if (wait_for((vlv_update_rps_cur_delay(dev_priv) &&
> + (dev_priv->rps.cur_delay ==
> + dev_priv->rps.rpe_delay)), 100))
> + DRM_DEBUG_DRIVER("Not able to set Rpe\n");
> +
> + } else {
> + /* When, Gfx clock is DOWN */
> +
> + /* Mask turbo interrupt so that they will not come in between */
> + I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
> +
> + /* Bring up the Gfx clock */
> + I915_WRITE(VLV_GTLC_SURVIVABILITY_REG,
> + I915_READ(VLV_GTLC_SURVIVABILITY_REG) |
> + VLV_GFX_CLK_FORCE_ON_BIT);
> +
> + if (wait_for(((VLV_GFX_CLK_STATUS_BIT &
> + I915_READ(VLV_GTLC_SURVIVABILITY_REG)) != 0), 500)) {
> + DRM_ERROR("GFX_CLK_ON request timed out\n");
> + return;
> + }
> +
> + vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
> + dev_priv->rps.rpe_delay);
> +
> + /* Make sure Rpe is set by P-Unit*/
> + if (wait_for((vlv_update_rps_cur_delay(dev_priv) &&
> + (dev_priv->rps.cur_delay ==
> + dev_priv->rps.rpe_delay)), 100))
> + DRM_DEBUG_DRIVER("Not able to set Rpe\n");
> +
> + /* Release the Gfx clock */
> + I915_WRITE(VLV_GTLC_SURVIVABILITY_REG,
> + I915_READ(VLV_GTLC_SURVIVABILITY_REG) &
> + ~VLV_GFX_CLK_FORCE_ON_BIT);
> +
> + /* Unmask Turbo interrupts */
> + I915_WRITE(GEN6_PMINTRMSK, ~GEN6_PM_RPS_EVENTS);
> + }
> +}
> +
> +
> void gen6_rps_idle(struct drm_i915_private *dev_priv)
> {
> mutex_lock(&dev_priv->rps.hw_lock);
> if (dev_priv->rps.enabled) {
> if (dev_priv->info->is_valleyview)
> - valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
> + vlv_set_rps_idle(dev_priv);
> else
> gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
> dev_priv->rps.last_adj = 0;
> @@ -4846,6 +4921,7 @@ void intel_gpu_ips_teardown(void)
> i915_mch_dev = NULL;
> spin_unlock_irq(&mchdev_lock);
> }
> +
> static void intel_init_emon(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> --
> 1.8.4.2
>
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--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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