[Intel-gfx] [PATCH 1/2] rendercopy/bdw: Emit 3DSTATE_WM_HZ_OP.

[Kenneth Graunke]

We don't want depth/stencil fast clears or HiZ resolves; we want normal
drawing.  Without this, the pixel pipeline doesn't work.

Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Cc: Ben Widawsky <ben at bwidawsk.net>
Cc: Damien Lespiau <damien.lespiau at intel.com>
---
 lib/gen8_render.h     |  2 ++
 lib/rendercopy_gen8.c | 10 ++++++++++
 2 files changed, 12 insertions(+)

diff --git a/lib/gen8_render.h b/lib/gen8_render.h
index 7b89876..ca53d64 100644
--- a/lib/gen8_render.h
+++ b/lib/gen8_render.h
@@ -22,6 +22,8 @@
 # define GEN8_3DSTATE_MULTISAMPLE_NUMSAMPLES_8			(3 << 1)
 # define GEN9_3DSTATE_MULTISAMPLE_NUMSAMPLES_16			(4 << 1)
 
+#define GEN8_3DSTATE_WM_HZ_OP			GEN6_3D(3, 0, 0x52)
+
 #define GEN8_3DSTATE_VF_INSTANCING		GEN6_3D(3, 0, 0x49)
 #define GEN7_3DSTATE_GS				GEN6_3D(3, 0, 0x11)
 #define GEN7_3DSTATE_CONSTANT_GS		GEN6_3D(3, 0, 0x16)
diff --git a/lib/rendercopy_gen8.c b/lib/rendercopy_gen8.c
index 1a137dd..38dc0e7 100644
--- a/lib/rendercopy_gen8.c
+++ b/lib/rendercopy_gen8.c
@@ -679,7 +679,17 @@ gen8_emit_ds(struct intel_batchbuffer *batch) {
 }
 
 static void
+gen8_emit_wm_hz_op(struct intel_batchbuffer *batch) {
+	OUT_BATCH(GEN8_3DSTATE_WM_HZ_OP | (5-2));
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+	OUT_BATCH(0);
+}
+
+static void
 gen8_emit_null_state(struct intel_batchbuffer *batch) {
+	gen8_emit_wm_hz_op(batch);
 	gen8_emit_hs(batch);
 	OUT_BATCH(GEN7_3DSTATE_TE | (4-2));
 	OUT_BATCH(0);
-- 
1.8.4.2