[Intel-gfx] [PATCH 0/5] drm/i915: Gen2 PLL fixes

[Bruno Prémont]

Hi Ville,

On Mon, 09 December 2013 ville.syrjala at linux.intel.com wrote:
> There appear to be some gen2 machines that don't really like the current PLL
> limits we have. We also have some accuracy problems with the PLL calculations.
> This series aims to eliminate those problems, and at least my 855 machine
> seems happier with these patches.
> 
> Ville Syrjälä (5):
>       drm/i915: Extract p2 divider correctly for gen2 LVDS dual channel
>       drm/i915: Change N divider minimum from 3 to 2 for gen2
>       drm/i915: Increase gen2 vco frequency limit to 1512 MHz
>       drm/i915: Fix 66 MHz LVDS SSC freq for gen2
>       drm/i915: Decrease gen2 vco frequency minimum to 908 MHz
> 
>  drivers/gpu/drm/i915/intel_bios.c    |  8 ++++----
>  drivers/gpu/drm/i915/intel_display.c | 34 +++++++++++++++++++---------------
>  2 files changed, 23 insertions(+), 19 deletions(-)

Here is my dmesg with the 5 patches applied (on top of 3.13-rc3 and
the PLL debug patch).

The WARN() are not hit anymore.

[    0.782919] [drm:intel_shared_dpll_init], 0 shared PLLs initialized
[    0.782925] vgaarb: device changed decodes: PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem
[    0.870218] [drm] GMBUS [i915 gmbus panel] timed out, falling back to bit banging on pin 3
...
[    0.966313] [drm:intel_dump_pipe_config], DPLL = 0x808b0000
[    0.966316] [drm:intel_dump_pipe_config], DPLL_MD = 0x0
[    0.966318] [drm:intel_dump_pipe_config], FP0 = 0x21207
[    0.966320] [drm:intel_dump_pipe_config], FP1 = 0x21207
...
[    0.966369] [drm:intel_dump_pipe_config], DPLL = 0x90020000
[    0.966371] [drm:intel_dump_pipe_config], DPLL_MD = 0x0
[    0.966373] [drm:intel_dump_pipe_config], FP0 = 0x2140e
[    0.966375] [drm:intel_dump_pipe_config], FP1 = 0x21207
...
[    1.020672] [drm:intel_dump_pipe_config], DPLL = 0x0
[    1.020674] [drm:intel_dump_pipe_config], DPLL_MD = 0x0
[    1.020677] [drm:intel_dump_pipe_config], FP0 = 0x0
[    1.020679] [drm:intel_dump_pipe_config], FP1 = 0x0
...
[    1.121981] fbcon: inteldrmfb (fb0) is primary device
[    1.122810] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
[    1.122817] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=0, fb_changed=0
...
[    1.122907] [drm:intel_dump_pipe_config], DPLL = 0x0
[    1.122908] [drm:intel_dump_pipe_config], DPLL_MD = 0x0
[    1.122910] [drm:intel_dump_pipe_config], FP0 = 0x0
[    1.122911] [drm:intel_dump_pipe_config], FP1 = 0x0
...
[    1.646702] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device
[    1.646765] i915 0000:00:02.0: registered panic notifier
[    1.646831] [drm] Initialized i915 1.6.0 20080730 for 0000:00:02.0 on minor 0
...
[   46.584578] [drm:intel_dump_pipe_config], DPLL = 0x0
[   46.584581] [drm:intel_dump_pipe_config], DPLL_MD = 0x0
[   46.584583] [drm:intel_dump_pipe_config], FP0 = 0x0
[   46.584586] [drm:intel_dump_pipe_config], FP1 = 0x0
...
[   69.216340] [drm:intel_dump_pipe_config], DPLL = 0x0
[   69.216342] [drm:intel_dump_pipe_config], DPLL_MD = 0x0
[   69.216345] [drm:intel_dump_pipe_config], FP0 = 0x0
[   69.216347] [drm:intel_dump_pipe_config], FP1 = 0x0
...
[   69.329866] [drm:intel_dump_pipe_config], DPLL = 0x0
[   69.329870] [drm:intel_dump_pipe_config], DPLL_MD = 0x0
[   69.329874] [drm:intel_dump_pipe_config], FP0 = 0x0
[   69.329878] [drm:intel_dump_pipe_config], FP1 = 0x0

Bruno
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