[Intel-gfx] [PATCH v2 2/2] drm/i915: Record BB_ADDR for every ring

[Daniel Vetter]

On Tue, Dec 10, 2013 at 09:44:43PM +0200, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> Every ring seems to have a BB_ADDR registers, so include them all in the
> error state.
> 
> v2: Also include the _UDW on BDW
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

Both merged to dinq, thanks.
-Daniel
> ---
>  drivers/gpu/drm/i915/i915_drv.h       |  2 +-
>  drivers/gpu/drm/i915/i915_gpu_error.c | 12 ++++++------
>  drivers/gpu/drm/i915/i915_reg.h       |  3 ++-
>  3 files changed, 9 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index efc57fe..60cc8e0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -323,7 +323,7 @@ struct drm_i915_error_state {
>  	u32 instps[I915_NUM_RINGS];
>  	u32 extra_instdone[I915_NUM_INSTDONE_REG];
>  	u32 seqno[I915_NUM_RINGS];
> -	u64 bbaddr;
> +	u64 bbaddr[I915_NUM_RINGS];
>  	u32 fault_reg[I915_NUM_RINGS];
>  	u32 done_reg;
>  	u32 faddr[I915_NUM_RINGS];
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 9a64292..a707cca 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -247,12 +247,11 @@ static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
>  	err_printf(m, "  IPEIR: 0x%08x\n", error->ipeir[ring]);
>  	err_printf(m, "  IPEHR: 0x%08x\n", error->ipehr[ring]);
>  	err_printf(m, "  INSTDONE: 0x%08x\n", error->instdone[ring]);
> -	if (ring == RCS && INTEL_INFO(dev)->gen >= 4)
> -		err_printf(m, "  BBADDR: 0x%08llx\n", error->bbaddr);
> -	if (INTEL_INFO(dev)->gen >= 4)
> +	if (INTEL_INFO(dev)->gen >= 4) {
> +		err_printf(m, "  BBADDR: 0x%08llx\n", error->bbaddr[ring]);
>  		err_printf(m, "  BB_STATE: 0x%08x\n", error->bbstate[ring]);
> -	if (INTEL_INFO(dev)->gen >= 4)
>  		err_printf(m, "  INSTPS: 0x%08x\n", error->instps[ring]);
> +	}
>  	err_printf(m, "  INSTPM: 0x%08x\n", error->instpm[ring]);
>  	err_printf(m, "  FADDR: 0x%08x\n", error->faddr[ring]);
>  	if (INTEL_INFO(dev)->gen >= 6) {
> @@ -725,8 +724,9 @@ static void i915_record_ring_state(struct drm_device *dev,
>  		error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
>  		error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
>  		error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
> -		if (ring->id == RCS)
> -			error->bbaddr = I915_READ(BB_ADDR);
> +		error->bbaddr[ring->id] = I915_READ(RING_BBADDR(ring->mmio_base));
> +		if (INTEL_INFO(dev)->gen >= 8)
> +			error->bbaddr[ring->id] |= (u64) I915_READ(RING_BBADDR_UDW(ring->mmio_base)) << 32;
>  		error->bbstate[ring->id] = I915_READ(RING_BBSTATE(ring->mmio_base));
>  	} else {
>  		error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2d20390..8828ee4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -734,6 +734,8 @@
>  #define HWSTAM		0x02098
>  #define DMA_FADD_I8XX	0x020d0
>  #define RING_BBSTATE(base)	((base)+0x110)
> +#define RING_BBADDR(base)	((base)+0x140)
> +#define RING_BBADDR_UDW(base)	((base)+0x168) /* gen8+ */
>  
>  #define ERROR_GEN6	0x040a0
>  #define GEN7_ERR_INT	0x44040
> @@ -924,7 +926,6 @@
>  #define   CM0_COLOR_EVICT_DISABLE (1<<3)
>  #define   CM0_DEPTH_WRITE_DISABLE (1<<1)
>  #define   CM0_RC_OP_FLUSH_DISABLE (1<<0)
> -#define BB_ADDR		0x02140 /* 8 bytes */
>  #define GFX_FLSH_CNTL	0x02170 /* 915+ only */
>  #define GFX_FLSH_CNTL_GEN6	0x101008
>  #define   GFX_FLSH_CNTL_EN	(1<<0)
> -- 
> 1.8.3.2
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch