[Intel-gfx] [PATCH 2/2] generate_test_batches: Add a MI_LOAD_REGISTER_IMM test batch

[Damien Lespiau]

Signed-off-by: Damien Lespiau <damien.lespiau at intel.com>
---
 tests/generate_test_batches.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/tests/generate_test_batches.c b/tests/generate_test_batches.c
index 997ce37..41f883d 100644
--- a/tests/generate_test_batches.c
+++ b/tests/generate_test_batches.c
@@ -87,6 +87,25 @@ static void emit_mi_flush_dw(struct intel_batchbuffer *batch)
 	batch_finish(batch, "gen8-2d-mi-flush-dw-len-4.batch");
 }
 
+#define MI_LOAD_REGISTER_IMM	(0x22<<23)
+
+/*
+ * Make sure we correctly print out addresses when the address field only
+ * specificies a number of bits (eg. 22:3). The value to decode is then:
+ *   val << 3
+ * and not just the raw field value.
+ */
+static void emit_mi_load_register_imm(struct intel_batchbuffer *batch)
+{
+	batch_start(batch);
+
+	OUT_BATCH(MI_LOAD_REGISTER_IMM | (3-2));
+	OUT_BATCH(0x0000227c);
+	OUT_BATCH(0);
+
+	batch_finish(batch, "gen8-3d-partial-addresses.batch");
+}
+
 static struct gen_batches {
 	int drm_fd;
 	uint32_t devid;
@@ -106,4 +125,5 @@ int main(int argc, char **argv)
 	igt_assert(batch);
 
 	emit_mi_flush_dw(batch);
+	emit_mi_load_register_imm(batch);
 }
-- 
1.8.3.1