[Intel-gfx] [RFC 10/13] drm/i915: MI_LOAD_REGISTER_IMM fix

[Lister, Ian]

From 8f392d11c51beb66e01a63af33d90cb0bf01eda4 Mon Sep 17 00:00:00 2001
Message-Id: <8f392d11c51beb66e01a63af33d90cb0bf01eda4.1387201899.git.ian.lister at intel.com>
In-Reply-To: <cover.1387201899.git.ian.lister at intel.com>
References: <cover.1387201899.git.ian.lister at intel.com>
From: ian-lister <ian.lister at intel.com>
Date: Tue, 10 Dec 2013 16:46:51 +0000
Subject: [RFC 10/13] drm/i915: MI_LOAD_REGISTER_IMM fix

There are comments in i915_reg.h that suggest that an MI_LOAD_REGISTER_IMM
should be immediately preceded by a MI_NOOP. Added missing MI_NOOPs to
i915_gen7_sol_offsets.

Signed-off-by: ian-lister <ian.lister at intel.com>
---
 drivers/gpu/drm/i915/i915_gem_execbuffer.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 885d595..c9d330a 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -937,14 +937,20 @@ i915_reset_gen7_sol_offsets(struct drm_device *dev,
 	if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS])
 		return 0;
 
-	ret = intel_ring_begin(ring, 4 * 3);
+	ret = intel_ring_begin(ring, 2 + (4 * 4));
 	if (ret)
 		return ret;
 
+	/* Comments in i915_reg.h indicate that a MI_LOAD_REGISTER_IMM
+	* should be preceded by a MI_NOOP */
+	intel_ring_emit(ring, MI_NOOP);
+	intel_ring_emit(ring, MI_NOOP);
+
 	for (i = 0; i < 4; i++) {
 		intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 		intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i));
 		intel_ring_emit(ring, 0);
+		intel_ring_emit(ring, MI_NOOP);
 	}
 
 	intel_ring_advance(ring);
-- 
1.8.5.1