[Intel-gfx] [ANNOUNCE] xf86-video-intel 2.99.907

Chris Wilson chris at chris-wilson.co.uk
Mon Dec 30 11:39:57 CET 2013


Snapshot 2.99.907 (2013-12-30)
==============================
The highlight here is that things seem to be quietening down on the bug
reporting front. All is not quiet as you will see below, and maybe it is
just the holiday season that is approaching*, but there has been a
remarkable falloff in bug reports. Lets hope this trend holds and we can
make a stable release shortly!

* This was intended to be sent a couple of weeks ago and the holiday season
has been very quiet....

Oh, and acceleration support for Intel's next generation of
integrated processor graphics has landed, codenamed Broadwell.

 * Fix potential X server infinite recursion (crash) from a gen2 bug fix
   Regression in 2.99.906
   https://bugs.freedesktop.org/show_bug.cgi?id=71605

 * Workaround a missing pipeline flush within Ivybridge, that would
   leave black rectangles randomly over the output
   https://bugs.freedesktop.org/show_bug.cgi?id=68410

 * Fix tiled fills. gen2-3 and gen4+ had two different bugs that
   both broke rendering with small 8x8 patterns in some circumstances
   https://bugs.freedesktop.org/show_bug.cgi?id=71260

 * Fix reads from a cropped video image using a packed pixel format.

 * Another clear the clear hint after DRI2 SwapBuffers, like the bug fixed
   in 2.99.903. Failure to clear the hint would cause read backs of the
   frontbuffer (Xvnc) to be blank.
   https://bugs.freedesktop.org/show_bug.cgi?id=72194

 * Disable VSync on Baytrail
   https://bugs.freedesktop.org/show_bug.cgi?id=69869

 * Handle partial uploads with TearFree correctly
   https://bugs.freedesktop.org/show_bug.cgi?id=72343
   https://bugs.freedesktop.org/show_bug.cgi?id=72430

 * Avoid recusing through DRI event handlers whilst processing TearFree,
   leading to a double free (and memory corruption)
   https://bugs.freedesktop.org/show_bug.cgi?id=72690

 * Hide the gen4 render corruption by crippling the GPU
   https://bugs.freedesktop.org/show_bug.cgi?id=55500


Complete list of changes since 2.99.906
---------------------------------------

Chris Wilson (86):
      sna: Eliminate a compiler warning for a shadowed variable
      sna: Eliminate a compiler warning for a shadowed variable
      tests: Add render-composite-solid-mask
      sna/gen6+: Improve debug PREFER_RENDER to cover all decision points
      sna/gen6+: Only substitute SRC for CLEAR if using the correct source
      tests: Exercise render copies under a mask
      sna: Add the missing braces around the conditional block
      sna: Include valgrind leakchecks for --enable-debug=memory
      sna/damage: Guard against integer overflow before malloc
      sna/damage: Tidy up a tail return
      tests: Avoid dependence on undefined C
      sna: Process Damage relative to dst->pDrawable not its pixmap->drawable
      sna: Tell valgrind about the returned mode list
      sna/gen7: Rework random GPU flushing
      test: Fix compilation of render-trapezoid-image
      sna/gen4+: Clear redirect bo before falling back to BLT paths
      sna: Correct check for overwriting last BLT fill
      sna: Free composite boxes in the unlikely all-invalid path
      sna: Fix use before assignment
      intel-virtual-output: Fix trivial and unlikely fd leak from bumblebee failure
      intel-virtual-output: Check for failure to create a clone
      sna/gen7: Try to reduce flushes between primitive continuations
      sna: Set supported rotations on virtual outputs
      sna: Fix typo in sna_blt_fill_begin()
      sna: XY_SETUP_* expects the dst tiling to be set on gen4+
      sna: Tidy up fallback from render composite to blt composite
      uxa,sna: Prevent bo exchange when pinned for non-DRI2 clients
      Revert "intel-virtual-output: Only track the most recent visibility status of the cursor"
      Correct type of uevent_handler
      sna/trapezoids: trapezoids_bounds() reports not-empty, so use it
      sna: Keep @NOWARNFLAGS@ last
      sna: Log mode switches on virtual outputs
      intel-virtual-output: Tweak DBG messages for copying rotation
      sna: Include reflections when logging mode changes
      intel-virtual-output: Include transforms when computing required fb size
      sna: Correct plurization of axis for modesetting log message
      intel-virtual-output: Correct clip region of rotated outputs in source framebuffer
      intel-virtual-output: Clone remote EDID for virtual outputs
      sna: Update connector-type-to-string mapping
      intel-virtual-output: Workaround mutter always using the same timestamp
      intel-virtual-output: Trim remote framebuffer to fit
      sna: Add a few more refcnt asserts
      sna: Wrap image upload with sigtrap
      sna: Tidy a split conditional in an picture upload
      sna: Prefer using userptr for PutImage into large GPU bo
      sna: Wrap glyph composition with sigtrap handling
      sna: Harden GetImage for use with very large buffers
      sna: Tidy up an assertion on an uninitialised variable
      sna: Fallback from partial to full move-to-cpu
      sna/video: Correct handling of cropped images along packed fast path
      sna: Fix typo inside DBG message
      sna: Dump GTT info if we fail to execute a batch due to ENOSPC
      tests: Exercise tiled fills
      sna: Drop forced alignment to 64 on pre-gen4 devices
      sna: Fix tile origin for pattern blits
      tests: Exercise stippled fills
      sna: Fix stipple offset for drawing into child windows
      sna: Include Pineview in fence over-allocation checks
      sna: Clear the clear hint after performing a userptr upload
      sna: More assertions around tracking mapped state
      sna: Mark up an ordinary pixmap for reuse
      sna/gen2,3: Unmap the old GPU bo when replacing due to render target constaints
      sna/dri: Always clear the clear hint after pageflipping
      intel: Tidy up driver identification string
      sna: Print detected GPU first
      sna: Update Baytrail VSync logic
      sna: Compilation fixes for squeeze
      configure: Correct closing ']'
      sna: OsRegisterSigWrapper was only introduced in 1.6.99.900
      sna: Pass MOVE_READ for partial TearFree move-to-gpu
      sna: Simplify kgem_bo_can_map()
      sna: Fallback gracefully when redisplaying after a GPU hang
      sna: Only discard READ hint for TearFree copy iff it subsumes the pixmap
      sna: Set minimum pitch alignment to 8 bytes
      sna/gen2,3: Replace stale bo replacement with simple asserts
      Update i915_pciids.h
      sna/gen8: Initial backend for Broadwell
      sna: Enable scanline waits for Broadwell
      intel: Recognise gen8
      sna: Remove unused variable
      sna/gen4+: Drop new assertion that we only finish a vbo after use in this batch
      sna: Avoid recursive out-of-order operations in the middle of TearFree
      intel-virtual-output: Disable build if timerfd is not present
      sna: Remove stale assertion
      sna/gen4: Sacrifice performance to workaround render corruption
      2.99.907 snapshot

Kirill Müller (1):
      intel-virtual-output: mute spurious warnings

Zdenek Kabelac (12):
      Makefile convert @var@ to $(var)
      config apostrophe
      Remove uneeded headers
      Cast to use unsigned math
      uxa: Ensure mask_picture is defined
      uxa: rename some local variable to not shadow global ones
      Fix indentation for incorrectly shifted statements
      uxa: Avoid relying on an assert and cleanup iterator
      sna: Add missing va_end
      uxa,legacy: use unsigned for comparition of unsigned
      uxa: fix order of inline Bool
      sna: Handle failure to disable old plane when switching CRTCs

git tag: 2.99.907

http://xorg.freedesktop.org/archive/individual/driver/xf86-video-intel-2.99.907.tar.bz2
MD5:  1e7011af0c2ec4103229b6cccd6e79a5  xf86-video-intel-2.99.907.tar.bz2
SHA1: 5759feef71aa09c82111090ff163fa5ba94406f6  xf86-video-intel-2.99.907.tar.bz2
SHA256: d0b02255f0ff4baa863f762bef49707ce0b4094a267a26e32e4270abe141117b  xf86-video-intel-2.99.907.tar.bz2

http://xorg.freedesktop.org/archive/individual/driver/xf86-video-intel-2.99.907.tar.gz
MD5:  e501aab41be5d6e3e4ee5255c6647498  xf86-video-intel-2.99.907.tar.gz
SHA1: 18e3b2f4f34311520c306725f349bf496184fd9c  xf86-video-intel-2.99.907.tar.gz
SHA256: 608705d30980693454fb68e86f489f2e76e4029f806efaeb38d48cacaa166282  xf86-video-intel-2.99.907.tar.gz

-- 
Chris Wilson, Intel Open Source Technology Centre
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