[Intel-gfx] [PATCH 03/22] drm/i915: add UCGCTL4 to display reg check on VLV

[Jesse Barnes]

Add a few regs needed for various clock gating init purposes and make
sure they don't fall into the display offset range on VLV.

Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_drv.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 69d0637..13b9b4f 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1208,6 +1208,7 @@ static bool IS_DISPLAYREG(u32 reg)
 	case GEN7_HALF_SLICE_CHICKEN1:
 	case GEN6_MBCTL:
 	case GEN6_UCGCTL2:
+	case GEN7_UCGCTL4:
 		return false;
 	default:
 		break;
-- 
1.7.9.5