[Intel-gfx] [PATCH 15/90] assembler: Rename bits3.id and bits3.fd

[Damien Lespiau]

As always, to sync with mesa.

Signed-off-by: Damien Lespiau <damien.lespiau at intel.com>
---
 assembler/brw_structs.h |    4 ++--
 assembler/disasm.c      |    6 +++---
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/assembler/brw_structs.h b/assembler/brw_structs.h
index 2815256..c442f4a 100644
--- a/assembler/brw_structs.h
+++ b/assembler/brw_structs.h
@@ -1599,8 +1599,8 @@ struct brw_instruction
        } generic_gen5;
 
       GLuint ud;
-      GLint id;
-      GLfloat fd;
+      GLint d;
+      GLfloat f;
    } bits3;
 
    char *first_reloc_target, *second_reloc_target; // first for JIP, second for UIP
diff --git a/assembler/disasm.c b/assembler/disasm.c
index 6260a4e..b6fdc2e 100644
--- a/assembler/disasm.c
+++ b/assembler/disasm.c
@@ -628,13 +628,13 @@ static int imm (FILE *file, GLuint type, struct brw_instruction *inst) {
 	format (file, "0x%08xUD", inst->bits3.ud);
 	break;
     case BRW_REGISTER_TYPE_D:
-	format (file, "%dD", inst->bits3.id);
+	format (file, "%dD", inst->bits3.d);
 	break;
     case BRW_REGISTER_TYPE_UW:
 	format (file, "0x%04xUW", (uint16_t) inst->bits3.ud);
 	break;
     case BRW_REGISTER_TYPE_W:
-	format (file, "%dW", (int16_t) inst->bits3.id);
+	format (file, "%dW", (int16_t) inst->bits3.d);
 	break;
     case BRW_REGISTER_TYPE_UB:
 	format (file, "0x%02xUB", (int8_t) inst->bits3.ud);
@@ -646,7 +646,7 @@ static int imm (FILE *file, GLuint type, struct brw_instruction *inst) {
 	format (file, "0x%08xV", inst->bits3.ud);
 	break;
     case BRW_REGISTER_TYPE_F:
-	format (file, "%-gF", inst->bits3.fd);
+	format (file, "%-gF", inst->bits3.f);
     }
     return 0;
 }
-- 
1.7.7.5