[Intel-gfx] [PATCH 00/10] Display error reporting

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni at intel.com>

Hi

This series is the first step to improve error reporting on our driver.

The first 3 patches were already sent to the list and they're a requirement for
the series (because of the relationship between our "unclaimed register" checks
and the display error interrupts).

Patch 4 just removes some code duplication and could be merged before
everything else.

Patches 5-7 are the complicated bits. They use the "I want to report Poison
interrupts" excuse, but the main goal of these 3 patches is: make sure our code
is prepared for a possible "interrupt tsunami", enable SERR_INT and enable
GEN7_ERR_INT. The big problem with GEN7_ERR_INT and SERR_INT is that you can't
enable/disable the specific sub-cases of this interrupt: either you enable all
of the error interrupts or you disable all of them.

Patches 8 and 9 are mainly about printing error messages. They try to make sure
dmesg won't be flooded in case the interrupt tsunami happens, but they still
leave GEN7_ERR_INT and SERR_INT enabled even if we decide to ignore some of the
interrupts, because this way we may detect one problem even if the other is
being ignored.

Patch 10 is just for my OCD.

After this series, enabling and printing more error interrupts will be easier.
So far, I tested this series on ILK, SNB and HSW and I haven't seen the "Poison"
interrupt message, but I have seen the "PCH transcoder FIFO underrun" message on
SNB and ILK, and this seems to be caused by wrong watermark values when using
multiple pipes. Future patches will fix the problems reported by the error
messages. I hope these error messages will help us identify, reproduce and fix
bugs in our driver.

Thanks,
Paulo

Paulo Zanoni (10):
  drm/i915: drm/i915: create macros for the "unclaimed register" checks
  drm/i915: use FPGA_DBG for the "unclaimed register" checks
  drm/i915: clear the FPGA_DBG_RM_NOCLAIM bit at driver init
  drm/i915: add ibx_irq_postinstall
  drm/i915: also disable south interrupts when handling them
  drm/i915: print PCH poison interrupts
  drm/i915: print Gen5+ CPU poison interrupts
  drm/i915: print PCH FIFO underrun interrupts
  drm/i915: print CPU FIFO underruns
  drm/i915: also POSTING_READ(DEIER) on ivybridge_irq_handler

 drivers/gpu/drm/i915/i915_dma.c      |    4 +
 drivers/gpu/drm/i915/i915_drv.c      |   24 ++--
 drivers/gpu/drm/i915/i915_drv.h      |    5 +
 drivers/gpu/drm/i915/i915_irq.c      |  217 ++++++++++++++++++++++++++--------
 drivers/gpu/drm/i915/i915_reg.h      |   18 ++-
 drivers/gpu/drm/i915/intel_display.c |   16 ++-
 6 files changed, 223 insertions(+), 61 deletions(-)

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1.7.10.4