[Intel-gfx] [PATCH 11/19] drm/i915: track dp target_clock in pipe_config

[Daniel Vetter]

We need it in the fdi m_n computation, which nicely kills almost
all ugly special cases in there.

v2: Add a massive comment in the code to explain this mess.

Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 25 +++----------------------
 drivers/gpu/drm/i915/intel_dp.c      |  1 +
 drivers/gpu/drm/i915/intel_drv.h     | 14 ++++++++++++++
 3 files changed, 18 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4ad4576..58936ef 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5203,25 +5203,9 @@ static void ironlake_fdi_set_m_n(struct drm_crtc *crtc)
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct drm_display_mode *adjusted_mode =
 		&intel_crtc->config.adjusted_mode;
-	struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
-	struct intel_encoder *intel_encoder, *edp_encoder = NULL;
 	struct intel_link_m_n m_n = {0};
 	int target_clock, lane, link_bw;
-	bool is_dp = false, is_cpu_edp = false;
-
-	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
-		switch (intel_encoder->type) {
-		case INTEL_OUTPUT_DISPLAYPORT:
-			is_dp = true;
-			break;
-		case INTEL_OUTPUT_EDP:
-			is_dp = true;
-			if (!intel_encoder_is_pch_edp(&intel_encoder->base))
-				is_cpu_edp = true;
-			edp_encoder = intel_encoder;
-			break;
-		}
-	}
+	uint32_t bps;
 
 	/* FDI is a binary signal running at ~2.7GHz, encoding
 	 * each output octet as 10 bits. The actual frequency
@@ -5232,11 +5216,8 @@ static void ironlake_fdi_set_m_n(struct drm_crtc *crtc)
 	 */
 	link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
 
-	/* [e]DP over FDI requires target mode clock instead of link clock. */
-	if (edp_encoder)
-		target_clock = intel_edp_target_clock(edp_encoder, mode);
-	else if (is_dp)
-		target_clock = mode->clock;
+	if (intel_crtc->config.has_dp_encoder)
+		target_clock = intel_crtc->config.dp_target_clock;
 	else
 		target_clock = adjusted_mode->clock;
 
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 37b2bd1..eaf437b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -795,6 +795,7 @@ found:
 	intel_dp->lane_count = lane_count;
 	adjusted_mode->clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
 	pipe_config->pipe_bpp = bpp;
+	pipe_config->dp_target_clock = target_clock;
 
 	DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
 		      intel_dp->link_bw, intel_dp->lane_count,
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 8c90a64..fee0bde 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -192,6 +192,20 @@ struct intel_crtc_config {
 	bool dither;
 	int pipe_bpp;
 	struct intel_link_m_n dp_m_n;
+	/**
+	 * This is a pretty horrible mess: For all other encoders we keep the
+	 * target clock of the adjusted mode in adjusted_mode->clock. This is
+	 * used for e.g. fdi link bw calculations. The exception is dp, where we
+	 * put the dp link clock into adjusted_mode->clock. Which makes very
+	 * little sense, safe that it made port pll handling a bit easier.
+	 *
+	 * Until the port clock mess is cleaned up, we need to keep the dp
+	 * target mode clock somewhere, so that the fdi link bw code can get at
+	 * it (instead of the fdi code gropping through intel_dp internals).
+	 * Note that the code is littered with small bugs where we pick the
+	 * wrong clock :(
+	 */
+	int dp_target_clock;
 	/* Used by SDVO (and if we ever fix it, HDMI). */
 	unsigned pixel_multiplier;
 };
-- 
1.7.11.7