[Intel-gfx] [PATCH] drm/i915: Set i9xx lvds clock limits according to specifications

[Chris Wilson]

On Wed, Feb 13, 2013 at 10:20:21PM +0100, Patrik Jakobsson wrote:
> The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and 5-9.
> Since we do all calculations based on them being register values (which are
> subtracted by 2) we need to specify them accordingly.
> 
> Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson at gmail.com>

Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre