[Intel-gfx] [PATCH v2] drm/i915: Fix PIPE_CONTROL DW/QW write through global GTT on IVB+

[Ben Widawsky]

On Thu, Feb 14, 2013 at 02:46:44PM -0800, Ben Widawsky wrote:
> On Thu, Feb 14, 2013 at 09:53:51PM +0200, ville.syrjala at linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > 
> > The bit controlling whether PIPE_CONTROL DW/QW write targets
> > the global GTT or PPGTT moved moved from DW 2 bit 2 to
> > DW 1 bit 24 on IVB.
> > 
> > I verified on IVB that the fix is in fact effective. Without the fix
> > none of the scratch writes actually landed in the pipe control page.
> > With the fix the writes show up correctly.
> > 
> > v2: move PIPE_CONTROL_GLOBAL_GTT_IVB setup to where other flags are set
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
> [snip]

Reading the bspec again... do we want to set bit 21?

-- 
Ben Widawsky, Intel Open Source Technology Center