[Intel-gfx] [PATCH] drm/i915: Kill pipestat[] cache

[Jani Nikula]

On Wed, 20 Feb 2013, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> Caching the PIPESTAT enable bits has been deemed pointless. Just
> read them from the register itself.

Reviewed-by: Jani Nikula <jani.nikula at intel.com>

>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
> Again one of those things for which I don't have hardware.
> So this is only compile tested!
>
>  drivers/gpu/drm/i915/i915_drv.h |  1 -
>  drivers/gpu/drm/i915/i915_irq.c | 41 +++++++++++++++++------------------------
>  2 files changed, 17 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index e95337c..62b15f8 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -905,7 +905,6 @@ typedef struct drm_i915_private {
>  	struct mutex dpio_lock;
>  
>  	/** Cached value of IMR to avoid reads in updating the bitfield */
> -	u32 pipestat[2];
>  	u32 irq_mask;
>  	u32 gt_irq_mask;
>  
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 18de788..6c53fb9 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -60,26 +60,30 @@ ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
>  void
>  i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
>  {
> -	if ((dev_priv->pipestat[pipe] & mask) != mask) {
> -		u32 reg = PIPESTAT(pipe);
> +	u32 reg = PIPESTAT(pipe);
> +	u32 pipestat = I915_READ(reg) & 0x7fff0000;
>  
> -		dev_priv->pipestat[pipe] |= mask;
> -		/* Enable the interrupt, clear any pending status */
> -		I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
> -		POSTING_READ(reg);
> -	}
> +	if ((pipestat & mask) == mask)
> +		return;
> +
> +	/* Enable the interrupt, clear any pending status */
> +	pipestat |= mask | (mask >> 16);
> +	I915_WRITE(reg, pipestat);
> +	POSTING_READ(reg);
>  }
>  
>  void
>  i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
>  {
> -	if ((dev_priv->pipestat[pipe] & mask) != 0) {
> -		u32 reg = PIPESTAT(pipe);
> +	u32 reg = PIPESTAT(pipe);
> +	u32 pipestat = I915_READ(reg) & 0x7fff0000;
>  
> -		dev_priv->pipestat[pipe] &= ~mask;
> -		I915_WRITE(reg, dev_priv->pipestat[pipe]);
> -		POSTING_READ(reg);
> -	}
> +	if ((pipestat & mask) == 0)
> +		return;
> +
> +	pipestat &= ~mask;
> +	I915_WRITE(reg, pipestat);
> +	POSTING_READ(reg);
>  }
>  
>  /**
> @@ -2069,9 +2073,6 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
>  		I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
>  		I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
>  
> -	dev_priv->pipestat[0] = 0;
> -	dev_priv->pipestat[1] = 0;
> -
>  	/* Hack for broken MSIs on VLV */
>  	pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
>  	pci_read_config_word(dev->pdev, 0x98, &msid);
> @@ -2201,9 +2202,6 @@ static int i8xx_irq_postinstall(struct drm_device *dev)
>  {
>  	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
>  
> -	dev_priv->pipestat[0] = 0;
> -	dev_priv->pipestat[1] = 0;
> -
>  	I915_WRITE16(EMR,
>  		     ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
>  
> @@ -2350,9 +2348,6 @@ static int i915_irq_postinstall(struct drm_device *dev)
>  	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
>  	u32 enable_mask;
>  
> -	dev_priv->pipestat[0] = 0;
> -	dev_priv->pipestat[1] = 0;
> -
>  	I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
>  
>  	/* Unmask the interrupts that we always want on. */
> @@ -2605,8 +2600,6 @@ static int i965_irq_postinstall(struct drm_device *dev)
>  	if (IS_G4X(dev))
>  		enable_mask |= I915_BSD_USER_INTERRUPT;
>  
> -	dev_priv->pipestat[0] = 0;
> -	dev_priv->pipestat[1] = 0;
>  	i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
>  
>  	/*
> -- 
> 1.7.12.4
>
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