[Intel-gfx] [PATCH] drm/i915: Handle untiled planes when computing their offsets

[Chris Wilson]

We trim the fb to fit the CRTC by computing the offset of that CRTC to
its nearest tile_row origin. This allows us to use framebuffers that are
larger than the CRTC limits without additional work.

However, we failed to compute the offset for a linear framebuffer
correctly as we treated its x-advance in whole tiles (instead of the
linear increment expected), leaving the CRTC misaligned with its
contents.

Fixes regression from commit c2c75131244507c93f812862fdbd4f3a37139401
Author: Daniel Vetter <daniel.vetter at ffwll.ch>
Date:   Thu Jul 5 12:17:30 2012 +0200

    drm/i915: adjust framebuffer base address on gen4+

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=61152
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter at ffwll.ch>
Cc: stable at vger.kernel.org
---
 drivers/gpu/drm/i915/intel_display.c |   14 +++++++++-----
 drivers/gpu/drm/i915/intel_drv.h     |    3 ++-
 drivers/gpu/drm/i915/intel_sprite.c  |    6 ++++--
 3 files changed, 15 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a3ca9a8..2a46f08 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1906,18 +1906,20 @@ void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
 
 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
  * is assumed to be a power-of-two. */
-unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
+unsigned long intel_gen4_compute_planar_offset(int *x, int *y,
+					       unsigned int tiling_mode,
 					       unsigned int bpp,
 					       unsigned int pitch)
 {
-	int tile_rows, tiles;
+	int tile_rows, tiles, tile_size;
 
 	tile_rows = *y / 8;
 	*y %= 8;
 	tiles = *x / (512/bpp);
 	*x %= 512/bpp;
 
-	return tile_rows * pitch * 8 + tiles * 4096;
+	tile_size = tiling_mode != I915_TILING_NONE ? 4096 : 512;
+	return (tile_rows * pitch * 8 + tiles * tile_size) & -4096;
 }
 
 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
@@ -1993,7 +1995,8 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 
 	if (INTEL_INFO(dev)->gen >= 4) {
 		intel_crtc->dspaddr_offset =
-			intel_gen4_compute_offset_xtiled(&x, &y,
+			intel_gen4_compute_planar_offset(&x, &y,
+							 obj->tiling_mode,
 							 fb->bits_per_pixel / 8,
 							 fb->pitches[0]);
 		linear_offset -= intel_crtc->dspaddr_offset;
@@ -2085,7 +2088,8 @@ static int ironlake_update_plane(struct drm_crtc *crtc,
 
 	linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
 	intel_crtc->dspaddr_offset =
-		intel_gen4_compute_offset_xtiled(&x, &y,
+		intel_gen4_compute_planar_offset(&x, &y,
+						 obj->tiling_mode,
 						 fb->bits_per_pixel / 8,
 						 fb->pitches[0]);
 	linear_offset -= intel_crtc->dspaddr_offset;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 3a671d5..f5ad87b 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -671,7 +671,8 @@ extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
 extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe,
 			 struct drm_display_mode *mode);
 
-extern unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
+extern unsigned long intel_gen4_compute_planar_offset(int *x, int *y,
+						      unsigned int tiling_mode,
 						      unsigned int bpp,
 						      unsigned int pitch);
 
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 03cfd62..ea90077 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -119,7 +119,8 @@ ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
 
 	linear_offset = y * fb->pitches[0] + x * pixel_size;
 	sprsurf_offset =
-		intel_gen4_compute_offset_xtiled(&x, &y,
+		intel_gen4_compute_planar_offset(&x, &y,
+						 obj->tiling_mode,
 						 pixel_size, fb->pitches[0]);
 	linear_offset -= sprsurf_offset;
 
@@ -292,7 +293,8 @@ ilk_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
 
 	linear_offset = y * fb->pitches[0] + x * pixel_size;
 	dvssurf_offset =
-		intel_gen4_compute_offset_xtiled(&x, &y,
+		intel_gen4_compute_planar_offset(&x, &y,
+						 obj->tiling_mode,
 						 pixel_size, fb->pitches[0]);
 	linear_offset -= dvssurf_offset;
 
-- 
1.7.10.4