[Intel-gfx] [PATCH 0/8] fdi/dp m_n reorg and a few other clock changes

[Daniel Vetter]

Hi all,

This here is a bit a grab-bag of changes, all around the clock handling in our
code. Originally I've wanted to push this further so that we can compute the
desired dpll settings in the pipe_config computation stage. We need that to
properly figure out pll sharing for atomic modeset. But it's messy, so this only
moves us a bit further.

Also contained in here is the hw state readout support infrastructure for pipe
configurations. It helps in simplifying things a bit, but otherwise not used for
a lot of things yet.

Cheers, Daniel

Daniel Vetter (8):
  drm/i915: clear up the fdi/dp set_m_n confusion
  drm/i915: move dp_m_n computation to dp_encoder->compute_config
  drm/i915: track dp target_clock in pipe_config
  drm/i915: rip out superflous is_dp&is_cpu_edp tracking
  drm/i915: add hw state readout/checking for pipe_config
  drm/i915: hw readout support for ->has_pch_encoders
  drm/i915: create pipe_config->dpll for clock state
  drm/i915: move dp clock computations to encoder->compute_config

 drivers/gpu/drm/i915/i915_drv.h      |   5 +
 drivers/gpu/drm/i915/intel_display.c | 527 +++++++++++++++++------------------
 drivers/gpu/drm/i915/intel_dp.c      | 115 ++++----
 drivers/gpu/drm/i915/intel_drv.h     |  30 +-
 4 files changed, 335 insertions(+), 342 deletions(-)

-- 
1.7.11.4