[Intel-gfx] [PATCH 6/6] drm/i915: More HSW PM clean up.

[Paulo Zanoni]

Hi

2013/2/25 Rodrigo Vivi <rodrigo.vivi at gmail.com>:
> This is the last cleaning up patch for HSW, letting render standby
> programming sequence like the documented one at HSW PM programing guide.
>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at gmail.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 9 ---------
>  1 file changed, 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d43e011..ef51174 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2749,16 +2749,7 @@ static void hsw_enable_rps(struct drm_device *dev)
>                    GEN6_RP_UP_BUSY_AVG |
>                    GEN7_RP_DOWN_IDLE_AVG);
>
> -       gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);

Looks like the line above is not even on the SNB docs, and git blame
shows it's a bug fix. I'll let Chris comment on that. Having a nice
comment explaining why that code is there would be good :)

> -
> -       /* requires MSI enabled */
>         I915_WRITE(GEN6_PMIER, GEN7_PM_DEFERRED_EVENTS);
> -       spin_lock_irq(&dev_priv->rps.lock);
> -       WARN_ON(dev_priv->rps.pm_iir != 0);
> -       I915_WRITE(GEN6_PMIMR, 0);
> -       spin_unlock_irq(&dev_priv->rps.lock);
> -       /* enable all PM interrupts */
> -       I915_WRITE(GEN6_PMINTRMSK, 0);

This is all part of the interrupt enabling: just changing PMIER is not
enough, you have to change the masks and possibly clear the IIR
register.

>
>         gen6_gt_force_wake_put(dev_priv);
>  }
> --
> 1.8.1.2
>
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-- 
Paulo Zanoni