[Intel-gfx] [PATCH 4/8] drm/i915: Setup EDP PSR AUX Registers

[Rodrigo Vivi]

From: Shobhit Kumar <shobhit.kumar at intel.com>

Signed-off-by: Shobhit Kumar <shobhit.kumar at intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi at gmail.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 49 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 49 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f0224f8..c35caf1 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1423,6 +1423,55 @@ static bool is_edp_psr(struct intel_dp *intel_dp)
 	return (is_edp(intel_dp) && (intel_dp->psr_dpcd[0] & 0x1));
 }
 
+static void intel_edp_psr_setup(struct intel_dp *intel_dp)
+{
+	struct drm_device *dev = intel_dp_to_dev(intel_dp);
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	uint32_t aux_clock_divider;
+	int precharge = 0x3;
+	int msg_size = 5;	/* Header(4) + Message(1) */
+
+	/* No need to setup if already done as these setting are persistent
+	 * until power states are entered */
+	if (intel_dp->psr_setup)
+		return;
+
+	/* Setup AUX registers */
+	/* Write command on DPCD 0x0600 */
+	I915_WRITE(EDP_PSR_AUX_DATA1, 0x80060000);
+
+	/* Set the state to normal operation D0 in DPCD 0x0600 */
+	I915_WRITE(EDP_PSR_AUX_DATA2, 0x01000000);
+
+	if (is_cpu_edp(intel_dp)) {
+		if (!IS_HASWELL(dev) && (IS_GEN6(dev) || IS_GEN7(dev)))
+			aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
+		else
+			/* CDCLK divided by 2 */
+			aux_clock_divider = ((I915_READ(CDCLK_FREQ) & CDCLK_FREQ_MASK) + 1)/2;
+	} else if (HAS_PCH_SPLIT(dev))
+		aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
+	else
+		aux_clock_divider = intel_hrawclk(dev) / 2;
+
+	I915_WRITE(EDP_PSR_AUX_CTL,
+		   DP_AUX_CH_CTL_TIME_OUT_400us |
+		   (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
+		   (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
+		   (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
+
+	/* Setup the debug register */
+	I915_WRITE(EDP_PSR_DEBUG_CTL, I915_READ(EDP_PSR_DEBUG_CTL) |
+			EDP_PSR_DEBUG_MASK_MEMUP |
+			EDP_PSR_DEBUG_MASK_HPD);
+
+	/* This flag can be made to 0 from pm code so as to reinitialize the
+	 * AUX register in case of power states, returning from which will not
+	 * maintain the AUX register settings
+	 */
+	intel_dp->psr_setup = 1;
+}
+
 static void intel_enable_dp(struct intel_encoder *encoder)
 {
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
-- 
1.7.11.7