[Intel-gfx] [PATCH 5/8] drm/i915: VBT Parsing for the PSR Feature Block for HSW
Daniel Vetter
daniel at ffwll.ch
Fri Jan 11 21:46:01 CET 2013
On Fri, Jan 11, 2013 at 05:57:54PM -0200, Rodrigo Vivi wrote:
> From: Shobhit Kumar <shobhit.kumar at intel.com>
>
> Parse and store useful information in i915_dev_private
>
> Signed-off-by: Shobhit Kumar <shobhit.kumar at intel.com>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi at gmail.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 8 ++++++++
> drivers/gpu/drm/i915/intel_bios.c | 30 ++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_bios.h | 20 +++++++++++++++++++-
> 3 files changed, 57 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index d2b93a4..6cb3439 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -751,6 +751,14 @@ typedef struct drm_i915_private {
> } edp;
> bool no_aux_handshake;
>
> +
> + /* PSR related info from VBT */
> + u8 full_link_state;
> + u8 wait_lines;
> + u8 idle_frames;
> + u16 wakeup_tp1;
> + u16 wakeup_tp2_tp3;
Recently started holy war of mine: Can we pls now shovel random piles of
things into dev_priv? Preferred would be if only intel_dp.c would need to
care about this, otherwise a meaningful substruct (with the struct
definition out of line) is the 2nd best option ...
-Daniel
> +
> int crt_ddc_pin;
> struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
> int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
> index 87e9b92..a5fa3c4 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -381,6 +381,35 @@ parse_general_definitions(struct drm_i915_private *dev_priv,
> }
> }
>
> +
> +static void
> +parse_edp_psr(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
> +{
> + struct bdb_psr_features *psr;
> + struct bdb_lvds_options *lvds_opts;
> + int index = 0;
> + lvds_opts = find_section(bdb, BDB_LVDS_OPTIONS);
> + if (!lvds_opts) {
> + DRM_DEBUG_KMS("No LVDS Options block found.\n");
> + return;
> + }
> +
> + index = lvds_opts->panel_type;
> +
> + psr = find_section(bdb, BDB_PSR_FEATURES);
> + if (!psr) {
> + DRM_DEBUG_KMS("No PSR feature block found.\n");
> + return;
> + }
> +
> + dev_priv->full_link_state = psr[index].link_disable;
> + dev_priv->wait_lines = psr[index].wait_lines;
> + dev_priv->idle_frames = psr[index].idle_frames;
> + dev_priv->wakeup_tp1 = psr[index].wakeup_tp1;
> + dev_priv->wakeup_tp2_tp3 = psr[index].wakeup_tp2;
> +}
> +
> +
> static void
> parse_sdvo_device_mapping(struct drm_i915_private *dev_priv,
> struct bdb_header *bdb)
> @@ -747,6 +776,7 @@ intel_parse_bios(struct drm_device *dev)
> parse_device_mapping(dev_priv, bdb);
> parse_driver_features(dev_priv, bdb);
> parse_edp(dev_priv, bdb);
> + parse_edp_psr(dev_priv, bdb);
>
> if (bios)
> pci_unmap_rom(pdev, bios);
> diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
> index 36e57f9..c1d39de 100644
> --- a/drivers/gpu/drm/i915/intel_bios.h
> +++ b/drivers/gpu/drm/i915/intel_bios.h
> @@ -80,7 +80,7 @@ struct vbios_data {
> #define BDB_EXT_MMIO_REGS 6
> #define BDB_SWF_IO 7
> #define BDB_SWF_MMIO 8
> -#define BDB_DOT_CLOCK_TABLE 9
> +#define BDB_PSR_FEATURES 9
> #define BDB_MODE_REMOVAL_TABLE 10
> #define BDB_CHILD_DEVICE_TABLE 11
> #define BDB_DRIVER_FEATURES 12
> @@ -263,6 +263,24 @@ struct bdb_lvds_options {
> u8 rsvd4;
> } __attribute__((packed));
>
> +struct bdb_psr_features {
> + /* psr_enable byte */
> + u8 link_disable:1;
> + u8 require_aux:1;
> + u8 rsvd1:6;
> +
> + /* panel wait times */
> + u8 idle_frames:4;
> + u8 wait_lines:3;
> + u8 rsvd2:1;
> +
> + /* TP1 wakeup time */
> + u16 wakeup_tp1;
> +
> + /* TP2 wakeup time */
> + u16 wakeup_tp2;
> +} __attribute__((packed));
> +
> /* LFP pointer table contains entries to the struct below */
> struct bdb_lvds_lfp_data_ptr {
> u16 fp_timing_offset; /* offsets are from start of bdb */
> --
> 1.7.11.7
>
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--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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