[Intel-gfx] [PATCH] drm/i915: Disable AsyncFlip performance optimisations

[Daniel Vetter]

On Mon, Jan 21, 2013 at 10:25:36PM +0200, Imre Deak wrote:
> On Sun, 2013-01-20 at 16:11 +0000, Chris Wilson wrote:
> > This is a required workarounds for all products, especially on gen6+
> > where it causes the command streamer to fail to parse instructions
> > following a WAIT_FOR_EVENT. We use WAIT_FOR_EVENT for synchronising
> > between the GPU and the display engines, and so this bit being unset may
> > cause hangs.
> > 
> > References: https://bugzilla.kernel.org/show_bug.cgi?id=52311
> > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> > Cc: stable at vger.kernel.org
> 
> Reviewed-by: Imre Deak <imre.deak at intel.com>

Picked up for -fixes, thanks for the patch.
-Daniel
> 
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h         |    1 +
> >  drivers/gpu/drm/i915/intel_ringbuffer.c |   19 +++++++++++++------
> >  2 files changed, 14 insertions(+), 6 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 8b81052..db1c034 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -536,6 +536,7 @@
> >  #define MI_MODE		0x0209c
> >  # define VS_TIMER_DISPATCH				(1 << 6)
> >  # define MI_FLUSH_ENABLE				(1 << 12)
> > +# define ASYNC_FLIP_PERF_DISABLE			(1 << 14)
> >  
> >  #define GEN6_GT_MODE	0x20d0
> >  #define   GEN6_GT_MODE_HI				(1 << 9)
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index ef68037..af7adb0 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -503,13 +503,20 @@ static int init_render_ring(struct intel_ring_buffer *ring)
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> >  	int ret = init_ring_common(ring);
> >  
> > -	if (INTEL_INFO(dev)->gen > 3) {
> > +	if (INTEL_INFO(dev)->gen > 3)
> >  		I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
> > -		if (IS_GEN7(dev))
> > -			I915_WRITE(GFX_MODE_GEN7,
> > -				   _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
> > -				   _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
> > -	}
> > +
> > +	/* We need to disable the AsyncFlip performance optimisations in order
> > +	 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
> > +	 * programmed to '1' on all products.
> > +	 */
> > +	if (INTEL_INFO(dev)->gen >= 6)
> > +		I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
> > +
> > +	if (IS_GEN7(dev))
> > +		I915_WRITE(GFX_MODE_GEN7,
> > +			   _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
> > +			   _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
> >  
> >  	if (INTEL_INFO(dev)->gen >= 5) {
> >  		ret = init_pipe_control(ring);
> 
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch