[Intel-gfx] [PATCH 22/33] drm/i915: Pipe palette registers need an offset on VLV

[Daniel Vetter]

On Thu, Jan 24, 2013 at 03:29:47PM +0200, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

I've noticed that the PALETTE moved around a bit for pch-split platforms
already, but otoh the palette support is quite enhanced there already, and
we don't bother with it. Which renders 10bpc a bit pointless. So I'll gulp
this one here.
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 15ecded..7c71622 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1169,8 +1169,8 @@
>   * Palette regs
>   */
>  
> -#define _PALETTE_A		0x0a000
> -#define _PALETTE_B		0x0a800
> +#define _PALETTE_A		(dev_priv->info->display_mmio_offset + 0xa000)
> +#define _PALETTE_B		(dev_priv->info->display_mmio_offset + 0xa800)
>  #define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B)
>  
>  /* MCH MMIO space */
> -- 
> 1.7.12.4
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch