[Intel-gfx] [PATCH 25/33] drm/i915: PLL and clock gating registers need an offset on VLV

[Daniel Vetter]

On Fri, Jan 25, 2013 at 5:20 PM, Ville Syrjälä
<ville.syrjala at linux.intel.com> wrote:
>> > DSPCLK_GATE_D is used in intel_i2c_quirk_set(). OTOH gma500 has the
>> > same code commented out, so it may be that we can skip it too. Anyone
>> > have more details on this quirk?
>>
>> Afaict that quirk is for pnv only.
>
> So, should we just kill it for other HW? At least it needs to be killed
> for VLV if we don't merge this hunk.

There's a


	/* When using bit bashing for I2C, this bit needs to be set to 1 */
	if (!IS_PINEVIEW(dev_priv->dev))
		return;

guard in the quirk function, hence why it's pnv-only. So nothing to
fix I think, or I'm blind again ;-)
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch