[Intel-gfx] [PATCH 5/5] drm/i915: Dynamically calculate dclv

[Ben Widawsky]

Directory CacheLine Valid controls which PDEs are held in the directory
cache. Each bit represents 16 PDEs (16 PDEs at 4 bytes per entry is 1
cacheline, and therefore, almost makes sense).

Since we can now have an aliasing PPGTT which isn't 2GB, theoretically,
we should also modify the DCLV value to fit accordingly.

Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 5 +++--
 drivers/gpu/drm/i915/i915_reg.h     | 1 -
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index d9af815..168583b 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -344,11 +344,12 @@ void i915_gem_init_ppgtt(struct drm_device *dev)
 	}
 
 	for_each_ring(ring, dev_priv, i) {
+		uint64_t dclv = ppgtt->mapped_size >> 26;
+		dclv = (1ULL << dclv) - 1;
 		if (INTEL_INFO(dev)->gen >= 7)
 			I915_WRITE(RING_MODE_GEN7(ring),
 				   _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
-
-		I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
+		I915_WRITE(RING_PP_DIR_DCLV(ring), dclv);
 		I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
 	}
 }
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 94a08b9..780a715 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -117,7 +117,6 @@
 #define RING_PP_DIR_BASE(ring)		((ring)->mmio_base+0x228)
 #define RING_PP_DIR_BASE_READ(ring)	((ring)->mmio_base+0x518)
 #define RING_PP_DIR_DCLV(ring)		((ring)->mmio_base+0x220)
-#define   PP_DIR_DCLV_2G		0xffffffff
 
 #define GAM_ECOCHK			0x4090
 #define   ECOCHK_SNB_BIT		(1<<10)
-- 
1.8.1.1