[Intel-gfx] [PATCH 3/9] drm/i915: Added SDP and VSC structures for handling PSR for eDP

[Jani Nikula]

On Wed, 30 Jan 2013, Rodrigo Vivi <rodrigo.vivi at gmail.com> wrote:
> From: Shobhit Kumar <shobhit.kumar at intel.com>
>
> Signed-off-by: Sateesh Kavuri <sateesh.kavuri at intel.com>
>
> v2: Modified and corrected the structures to be more in line for
> kernel coding guidelines and rebased the code on Paulo's DP patchset
>
> Signed-off-by: Shobhit Kumar <shobhit.kumar at intel.com>
>
> v3: removing unecessary identation at DP_RECEIVER_CAP_SIZE
> v4: moving them to include/drm/drm_dp_helper.h and also already
>     icluding EDP_PSR_RECEIVER_CAP_SIZE to add everything needed
>     for PSR at once at drm_dp_helper.h
>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at gmail.com>
> ---
>  include/drm/drm_dp_helper.h | 29 +++++++++++++++++++++++++++++
>  1 file changed, 29 insertions(+)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index e8e1417..e9b7c4b 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -343,12 +343,41 @@ u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE],
>  					  int lane);
>  
>  #define DP_RECEIVER_CAP_SIZE	0xf
> +#define EDP_PSR_RECEIVER_CAP_SIZE      2
> +
>  void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]);
>  void drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]);
>  
>  u8 drm_dp_link_rate_to_bw_code(int link_rate);
>  int drm_dp_bw_code_to_link_rate(u8 link_bw);
>  
> +/* SDP header as per eDP 1.3 spec, section 3.6 */

Section 3.5.

> +struct edp_sdp_header {
> +	u8 id;
> +	u8 type;
> +	u8 revision : 5;   	    /* Bits 0:4 */
> +	u8 rsvd1    : 3;   	    /* Bits 5:7 */
> +	u8 valid_payload_bytes : 5; /* Bits 0:4 */
> +	u8 rsvd2	       : 3; /* Bits 5:7 */
> +} __attribute__((packed));
> +
> +/* SDP VSC header as per eDP 1.3 spec, section 3.6 */

Section 3.5.

I really wouldn't mind SDP and VSC being spelled out for the casual
reader without eDP spec at hand.

> +struct edp_vsc_psr {
> +	struct edp_sdp_header sdp_header;
> +	u8 unused;
> +	u8 psr_state  : 1; 	/* Bit 0 */
> +	u8 update_rfb : 1;	/* Bit 1 */
> +	u8 valid_crc  : 1;	/* Bit 2 */
> +	u8 reserved1  : 5;	/* Bits 3:7 */

I don't think the bitfields here are portable for representing the
data. A bit of googling suggests GCC lays out the bits as you document
above on little-endian machines, but the other way around on big-endian
machines. That would be fine within i915 which assumes little-endian for
obvious reasons, but not in common drm code.

I think you'll just have to use u8 and #defines for the bits and masks.


BR,
Jani.

> +	u8 crc_r_lower;
> +	u8 crc_r_higher;
> +	u8 crc_g_lower;
> +	u8 crc_g_higher;
> +	u8 crc_b_lower;
> +	u8 crc_b_higher;
> +	u8 reserved2[24];
> +} __attribute__((packed));
> +
>  static inline int
>  drm_dp_max_link_rate(u8 dpcd[DP_RECEIVER_CAP_SIZE])
>  {
> -- 
> 1.7.11.7
>
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