[Intel-gfx] [PATCH 10/35] drm/i915: Don't multiply the watermark latency values too early

[ville.syrjala at linux.intel.com]

From: Ville Syrjälä <ville.syrjala at linux.intel.com>

The LP1+ watermark latency values need to be multiplied by 5 to
make the suitable for watermark calculations. However on pre-HSW
platforms we're going to need the raw value later when we have to
write it to the WM_LPn registers' latency field. So delay the
multiplication until it's needed.

Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c266e47..a2ca018 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2346,10 +2346,10 @@ static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
 		wm[0] = (sskpd >> 56) & 0xFF;
 		if (wm[0] == 0)
 			wm[0] = sskpd & 0xF;
-		wm[1] = ((sskpd >> 4) & 0xFF) * 5;
-		wm[2] = ((sskpd >> 12) & 0xFF) * 5;
-		wm[3] = ((sskpd >> 20) & 0x1FF) * 5;
-		wm[4] = ((sskpd >> 32) & 0x1FF) * 5;
+		wm[1] = (sskpd >> 4) & 0xFF;
+		wm[2] = (sskpd >> 12) & 0xFF;
+		wm[3] = (sskpd >> 20) & 0x1FF;
+		wm[4] = (sskpd >> 32) & 0x1FF;
 	}
 }
 
@@ -2427,7 +2427,7 @@ static void hsw_compute_wm_results(struct drm_device *dev,
 	int level, max_level, wm_lp;
 
 	for (level = 1; level <= 4; level++)
-		if (!hsw_compute_lp_wm(wm[level], lp_maximums, params,
+		if (!hsw_compute_lp_wm(wm[level] * 5, lp_maximums, params,
 				       &lp_results[level - 1]))
 			break;
 	max_level = level - 1;
-- 
1.8.1.5