[Intel-gfx] [PATCH 09/35] drm/i915: Split out reading of HSW watermark latency values

[Ville Syrjälä]

On Fri, Jul 05, 2013 at 10:19:29AM +0100, Chris Wilson wrote:
> On Fri, Jul 05, 2013 at 11:57:21AM +0300, ville.syrjala at linux.intel.com wrote:
> > @@ -2593,10 +2598,11 @@ static void haswell_update_wm(struct drm_device *dev)
> >  	struct hsw_wm_maximums lp_max_1_2, lp_max_5_6;
> >  	struct hsw_pipe_wm_parameters params[3];
> >  	struct hsw_wm_values results_1_2, results_5_6, *best_results;
> > -	uint16_t wm[5];
> > +	uint16_t wm[5] = {};
> 
> Trying to hide a warning?

It's actually for the future ILK/SNB/IVB patches where we won't have
latency values for all 5 levels. I guess it should have been part of
those patches instead.

-- 
Ville Syrjälä
Intel OTC