[Intel-gfx] [PATCH 1/3] drm/i915: unify PM interrupt preinstall sequence

[Ben Widawsky]

On Fri, Jul 12, 2013 at 10:43:25PM +0200, Daniel Vetter wrote:
> Since the addition of VECS we have a slightly different enable
> sequence for PM interrupts on ivb/hsw vs snb and vlv. Usually that
> will end up in hard to track down surprises.
> 
> Hence unifiy things and since we have copies of this code in 3 places
> now, extract it into its own little helper.
> 
> Note that this changes the irq preinstall sequence a bit for snb and
> vlv: We now also clear the PM registers in the preinstall hook, in
> addition to the PM register clearing/setup already done when actually
> enabling rps. So this doesn't fix a bug but simply unifies the code
> across all platforms. After the postinstall hook is similarly unified
> we can rip out the then redundant PM interrupt setup from the rps
> code.
> 
> v3: Rebase on top of the retained double-GTIIR clearing. Also
> resurrect the masking/disabling of the gen6+ PM interrupts as spotted
> by Ben Widaswky.
> 
> v4: Move the DE interrupt reset code out of gen5_gt_irq_preinstall
> back to ironlake_irq_preinstall where it really belongs. Spotted by
> Paulo.
> 
> v3: Improve the commit message to more clearly spell out why we want
> to unify the code and what exactly changes.
> 
> Cc: Paulo Zanoni <przanoni at gmail.com>
> Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 39 +++++++++++++++++++++------------------
>  1 file changed, 21 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index cf1a21a..d5c3bef 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2583,6 +2583,23 @@ static void ibx_irq_preinstall(struct drm_device *dev)
>  	POSTING_READ(SDEIER);
>  }
>  
> +static void gen5_gt_irq_preinstall(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +
> +	/* and GT */
> +	I915_WRITE(GTIMR, 0xffffffff);
> +	I915_WRITE(GTIER, 0x0);
> +	POSTING_READ(GTIER);
> +
> +	if (INTEL_INFO(dev)->gen >= 6) {
> +		/* and GT */

and PM?
-- 
Ben Widawsky, Intel Open Source Technology Center