[Intel-gfx] [PATCH 2/3] drm/i915: unify GT/PM irq postinstall code

[Daniel Vetter]

On Sun, Jul 14, 2013 at 05:13:34PM -0700, Ben Widawsky wrote:
> On Sun, Jul 14, 2013 at 11:31:29PM +0200, Daniel Vetter wrote:
> > On Sun, Jul 14, 2013 at 01:55:20PM -0700, Ben Widawsky wrote:
> > > On Fri, Jul 12, 2013 at 10:43:26PM +0200, Daniel Vetter wrote:
> [snip]
> 
> > > 
> > > Maybe while you're doing this, explain why the L3 parity interrupt is
> > > special, in a comment. It's the only one to touch dev_priv->gt_irq_mask
> > 
> > I'll add 
> > 		/* L3 parity interrupt is always unmasked. */
> > 
> > before the gt_irq_mask assignemnt.
> 
> Actually, I was thinking more along the lines of "L3 parity interrupt is
> always unmasked. L3 parity interrupts are asynchronous with regard to
> batch submission, however they are delivered through ring interrupt
> registers."

We have more suche cases now with VECS going through PM interrupts. So I
don't think the fact that hw engineers sometimes steal bits from odd
places requires special mention. So I've opted for the simple version.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch