[Intel-gfx] [PATCH 04/11] drm/i915: Enable/Disable PSR

[Daniel Vetter]

On Wed, Jul 17, 2013 at 02:02:58PM -0300, Paulo Zanoni wrote:
> 2013/7/11 Rodrigo Vivi <rodrigo.vivi at gmail.com>:
> > +static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
> > +                                   struct edp_vsc_psr *vsc_psr)
> > +{
> > +       struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> > +       struct drm_device *dev = dig_port->base.base.dev;
> > +       struct drm_i915_private *dev_priv = dev->dev_private;
> > +       struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
> > +       u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
> > +       u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
> > +       uint32_t *data = (uint32_t *) vsc_psr;
> > +       unsigned int i;
> > +
> > +       /* As per BSPec (Pipe Video Data Island Packet), we need to disable
> > +          the video DIP being updated before program video DIP data buffer
> > +          registers for DIP being updated. */
> > +       I915_WRITE(ctl_reg, ~VIDEO_DIP_ENABLE_VSC_HSW);
> 
> This should be zero.With that fixed:

Fixed while applying.

> Reviewed-by: Paulo Zanoni <paulo.r.zanoni at intel.com>

Bikeshed: We now have two pieces of code writing DIPs, the other copy is
in intel_hdmi.c. And they don't match.

Slightly related, but: I'd really like to see our conversion to the common
infoframe helpers rsn ...

Cheers, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch