[Intel-gfx] [PATCH] Revert "drm/i915: Implement WaSwitchSolVfFArbitrationPriority"

[Daniel Vetter]

On Sun, Jul 21, 2013 at 01:49:16PM +0100, Chris Wilson wrote:
> This reverts commit e3dff585508636c8d2915cc1595e04f16ccd66ba.
> 
> The bspec recommends that this only be setup as part of the context for
> GPGPU as it penalizes 3D workloads. As we have exactly zero GPGPU
> clients at present, optimizing for them makes no sense.
> 
> The description from the bspec on how the driver should setup the memory
> hints is as follows:
>   "As part of the memory interface programming another option is to
>   re-allocate TLBs between different streams of GFX. The GFX TLBs are
>   organized as assigned resources for dedicated ports which could be
>   re-programmed based on the context that is being executed. This is
>   especially critical for the L3 backed clients which are seeing one large
>   TLB. The default programming favors 3D workloads (384 entry for
>   Textures, 64 entry for data port, 64 entry for rest), however for GPGPU
>   recommended setting is (64 for textures, 384 for dataport, 64 for rest).
>   With this new setting there are certain GPGPU workloads which benefit
>   significantly. Driver needs to make this setting part of the context
>   that is submitted. "
> 
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Ben Widawsky <ben at bwidawsk.net>

Cc: stable at vger.kernel.org

... since the offending commit is already in 3.10.
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 14 +++++++++++++-
>  1 file changed, 13 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 4e6d618..e1a4e4b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4662,8 +4662,20 @@ static void haswell_init_clock_gating(struct drm_device *dev)
>  	I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
>  		   GEN6_MBCTL_ENABLE_BOOT_FETCH);
>  
> -	/* WaSwitchSolVfFArbitrationPriority:hsw */
> +#if 0
> +	/* The default programming of GAM_ECOCHK favours 3D workloads (384
> +	 * entries for texturing, 64 for dataport and 64 for the rest).
> +	 * However, GPGPU workloads benefit greatly from an increased number
> +	 * of dataport entries. Setting ARB_PRIO_SOL here adjusts the TLB
> +	 * cache configuration to (64 for texturing, 384 for data and 64 for
> +	 * the rest) thereby favouring GPGPU over 3D workloads. By default
> +	 * we want to favour 3D workloads, but we should consider making this
> +	 * part of the context state for OpenCL clients.
> +	 *
> +	 * WaSwitchSolVfFArbitrationPriority:hsw
> +	 */
>  	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
> +#endif
>  
>  	/* WaRsPkgCStateDisplayPMReq:hsw */
>  	I915_WRITE(CHICKEN_PAR1_1,
> -- 
> 1.8.3.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch