[Intel-gfx] [PATCH 4/4] drm/i915: add HAS_LP_PCH check

[Daniel Vetter]

On Tue, Jul 23, 2013 at 11:19:27AM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni at intel.com>
> 
> We have 2 possible LPT PCHs: the normal version, which contains the
> pixel path (FDI, transcoders, VGA, etc), and the LP version, which
> comes with ULT machines and doesn't contain the pixel path. Both
> models return true for HAS_PCH_LPT.
> 
> We already have a few places where we explicitly check for LPT-LP, so
> add a HAS_LP_PCH check to simplify the code.
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>

Hm, I'm not that much convinced that this cleans up things: If we'll have
more LP versions in future generations then either the check will get ugly
or we have a bit a confusion. Since the scope of this chekc is fairly
restricted to a bit of reference clock handling I think we're ok.

One thing we could do is trim the giant suffix a bit, i.e.
s/INTEL_PCH_LPT_LP_DEVICE_ID_TYPE/INTEL_PCH_LPT_LP/. Since we're always
comparing that constant against a pciid or pch_id field it's still rather
clear what's going on. But like I've said, since this has fairly minimal
scope imo not really worth to make a fuss about.

So punted on this one here for now, but merged the other three patches
from this series.

Thanks, Daniel
> ---
>  drivers/gpu/drm/i915/i915_drv.h      | 2 ++
>  drivers/gpu/drm/i915/intel_display.c | 9 +++------
>  drivers/gpu/drm/i915/intel_pm.c      | 4 ++--
>  3 files changed, 7 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 8b3167e..713e7bc 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1575,6 +1575,8 @@ struct drm_i915_file_private {
>  #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
>  #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
>  #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
> +#define HAS_LP_PCH(dev_priv) ((dev_priv)->pch_id == \
> +				INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
>  
>  #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
>  
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 0b0696a..04a4550 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5274,8 +5274,7 @@ static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
>  
>  	if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
>  		with_spread = true;
> -	if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
> -		 with_fdi, "LP PCH doesn't have FDI\n"))
> +	if (WARN(HAS_LP_PCH(dev_priv) && with_fdi, "LP PCH doesn't have FDI\n"))
>  		with_fdi = false;
>  
>  	mutex_lock(&dev_priv->dpio_lock);
> @@ -5298,8 +5297,7 @@ static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
>  		}
>  	}
>  
> -	reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
> -	       SBI_GEN0 : SBI_DBUFF0;
> +	reg = HAS_LP_PCH(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
>  	tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
>  	tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
>  	intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
> @@ -5315,8 +5313,7 @@ static void lpt_disable_clkout_dp(struct drm_device *dev)
>  
>  	mutex_lock(&dev_priv->dpio_lock);
>  
> -	reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
> -	       SBI_GEN0 : SBI_DBUFF0;
> +	reg = HAS_LP_PCH(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
>  	tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
>  	tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
>  	intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 008e0e0..545d4ac 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4650,7 +4650,7 @@ static void lpt_init_clock_gating(struct drm_device *dev)
>  	 * TODO: this bit should only be enabled when really needed, then
>  	 * disabled when not needed anymore in order to save power.
>  	 */
> -	if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
> +	if (HAS_LP_PCH(dev_priv))
>  		I915_WRITE(SOUTH_DSPCLK_GATE_D,
>  			   I915_READ(SOUTH_DSPCLK_GATE_D) |
>  			   PCH_LP_PARTITION_LEVEL_DISABLE);
> @@ -4665,7 +4665,7 @@ static void lpt_suspend_hw(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
> -	if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
> +	if (HAS_LP_PCH(dev_priv)) {
>  		uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
>  
>  		val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
> -- 
> 1.8.1.2
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch