[Intel-gfx] [PATCH 03/15] drm/i915: port i965_irq_uninstall go INTEL_IRQ_REG_RESET

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni at intel.com>

The problem here is that we have the PIPESTAT registers between IER
and IIR, so when we use intel_irq_reg_reset we flip the order used to
reset IIR and PIPESTAT. That should be safe since after we clear
IMR/IER we won't get any other IIR/PIPESTAT interrupts. Still, the
change is on its own patch, so it should be easy to bisect and revert
if needed.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 292337b..b1b6552 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2920,13 +2920,11 @@ static void i965_irq_uninstall(struct drm_device * dev)
 	I915_WRITE(HWSTAM, 0xffffffff);
 	for_each_pipe(pipe)
 		I915_WRITE(PIPESTAT(pipe), 0);
-	I915_WRITE(IMR, 0xffffffff);
-	I915_WRITE(IER, 0x0);
+	INTEL_IRQ_REG_RESET(I, true);
 
 	for_each_pipe(pipe)
 		I915_WRITE(PIPESTAT(pipe),
 			   I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
-	I915_WRITE(IIR, I915_READ(IIR));
 }
 
 static void i915_reenable_hotplug_timer_func(unsigned long data)
-- 
1.8.1.2