[Intel-gfx] [PATCH 05/15] drm/i915: add INTEL_IRQ_REG_INIT

[Paulo Zanoni]

From: Paulo Zanoni <paulo.r.zanoni at intel.com>

Same reason as intel_irq_reg_reset: let's standardize the way we init
registers so we make sure all the code is doing the same thing, and
then we can also change everybody at the same time if we need. This
function is for irq_postinstall functions. Again, this patch only
converts the cases where the new code perfectly matches the old one,
other cases will be done in separate patches for better bisectability.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 30 ++++++++++++++----------------
 1 file changed, 14 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 29eac7a..e416848 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -92,6 +92,14 @@ static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
 	} \
 } while (0)
 
+#define INTEL_IRQ_REG_INIT(type, do_iir, ier_val, imr_val) do { \
+	if (do_iir) \
+		I915_WRITE(type##IR, I915_READ(type##IR)); \
+	I915_WRITE(type##MR, (imr_val)); \
+	I915_WRITE(type##ER, (ier_val)); \
+	POSTING_READ(type##ER); \
+} while (0)
+
 /* For display hotplug interrupt */
 static void
 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
@@ -2145,10 +2153,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
 		gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
 	}
 
-	I915_WRITE(GTIIR, I915_READ(GTIIR));
-	I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
-	I915_WRITE(GTIER, gt_irqs);
-	POSTING_READ(GTIER);
+	INTEL_IRQ_REG_INIT(GTI, true, gt_irqs, dev_priv->gt_irq_mask);
 
 	if (INTEL_INFO(dev)->gen >= 6) {
 		pm_irqs |= GEN6_PM_RPS_EVENTS;
@@ -2156,10 +2161,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
 		if (HAS_VEBOX(dev))
 			pm_irqs |= PM_VEBOX_USER_INTERRUPT;
 
-		I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
-		I915_WRITE(GEN6_PMIMR, 0xffffffff);
-		I915_WRITE(GEN6_PMIER, pm_irqs);
-		POSTING_READ(GEN6_PMIER);
+		INTEL_IRQ_REG_INIT(GEN6_PMI, true, pm_irqs, 0xffffffff);
 	}
 }
 
@@ -2189,11 +2191,8 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
 
 	dev_priv->irq_mask = ~display_mask;
 
-	/* should always can generate irq */
-	I915_WRITE(DEIIR, I915_READ(DEIIR));
-	I915_WRITE(DEIMR, dev_priv->irq_mask);
-	I915_WRITE(DEIER, display_mask | extra_mask);
-	POSTING_READ(DEIER);
+	INTEL_IRQ_REG_INIT(DEI, true, display_mask | extra_mask,
+			   dev_priv->irq_mask);
 
 	gen5_gt_irq_postinstall(dev);
 
@@ -2519,9 +2518,7 @@ static int i915_irq_postinstall(struct drm_device *dev)
 		dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
 	}
 
-	I915_WRITE(IMR, dev_priv->irq_mask);
-	I915_WRITE(IER, enable_mask);
-	POSTING_READ(IER);
+	INTEL_IRQ_REG_INIT(I, false, enable_mask, dev_priv->irq_mask);
 
 	i915_enable_asle_pipestat(dev);
 
@@ -2751,6 +2748,7 @@ static int i965_irq_postinstall(struct drm_device *dev)
 	I915_WRITE(IMR, dev_priv->irq_mask);
 	I915_WRITE(IER, enable_mask);
 	POSTING_READ(IER);
+	INTEL_IRQ_REG_INIT(I, false, enable_mask, dev_priv->irq_mask);
 
 	I915_WRITE(PORT_HOTPLUG_EN, 0);
 	POSTING_READ(PORT_HOTPLUG_EN);
-- 
1.8.1.2