[Intel-gfx] [PATCH 1/2] drm/i915: split PCI IDs out into i915_drm.h
Daniel Vetter
daniel at ffwll.ch
Thu Jul 25 00:14:14 CEST 2013
On Wed, Jul 24, 2013 at 10:22:48AM -0700, Jesse Barnes wrote:
> For use by userspace (at some point in the future) and other kernel code.
>
> Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
Note that this split isn't too useful for userspace in newer generations.
We still have the desktop/mobile split with since about ilk is meaningless
for actual kernel code. Only recently with the haswell ult this changed
again, but it's actually a different split. And userspace cares about gt1,
gt2, ... for threads counts, which is not something too important in
kernel land.
But the approach looks really good for sharing the table in the kernel, so
I'm fine with it.
-Daniel
> ---
> drivers/gpu/drm/i915/i915_drv.c | 158 ++++++----------------------------
> include/drm/i915_drm.h | 180 +++++++++++++++++++++++++++++++++++++++
> 2 files changed, 208 insertions(+), 130 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index b07362f..3834056 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -140,25 +140,6 @@ MODULE_PARM_DESC(fastboot, "Try to skip unnecessary mode sets at boot time "
> static struct drm_driver driver;
> extern int intel_agp_enabled;
>
> -#define INTEL_VGA_DEVICE(id, info) { \
> - .class = PCI_BASE_CLASS_DISPLAY << 16, \
> - .class_mask = 0xff0000, \
> - .vendor = 0x8086, \
> - .device = id, \
> - .subvendor = PCI_ANY_ID, \
> - .subdevice = PCI_ANY_ID, \
> - .driver_data = (unsigned long) info }
> -
> -#define INTEL_QUANTA_VGA_DEVICE(info) { \
> - .class = PCI_BASE_CLASS_DISPLAY << 16, \
> - .class_mask = 0xff0000, \
> - .vendor = 0x8086, \
> - .device = 0x16a, \
> - .subvendor = 0x152d, \
> - .subdevice = 0x8990, \
> - .driver_data = (unsigned long) info }
> -
> -
> static const struct intel_device_info intel_i830_info = {
> .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
> .has_overlay = 1, .overlay_needs_physical = 1,
> @@ -333,118 +314,35 @@ static const struct intel_device_info intel_haswell_m_info = {
> .has_vebox_ring = 1,
> };
>
> +#define INTEL_PCI_IDS \
> + INTEL_I830_IDS(&intel_i830_info), \
> + INTEL_I845G_IDS(&intel_845g_info), \
> + INTEL_I85X_IDS(&intel_i85x_info), \
> + INTEL_I865G_IDS(&intel_i865g_info), \
> + INTEL_I915G_IDS(&intel_i915g_info), \
> + INTEL_I915GM_IDS(&intel_i915gm_info), \
> + INTEL_I945G_IDS(&intel_i945g_info), \
> + INTEL_I945GM_IDS(&intel_i945gm_info), \
> + INTEL_I965G_IDS(&intel_i965g_info), \
> + INTEL_G33_IDS(&intel_g33_info), \
> + INTEL_I965GM_IDS(&intel_i965gm_info), \
> + INTEL_GM45_IDS(&intel_gm45_info), \
> + INTEL_G45_IDS(&intel_g45_info), \
> + INTEL_PINEVIEW_IDS(&intel_pineview_info), \
> + INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), \
> + INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), \
> + INTEL_SNB_D_IDS(&intel_sandybridge_d_info), \
> + INTEL_SNB_M_IDS(&intel_sandybridge_m_info), \
> + INTEL_IVB_M_IDS(&intel_ivybridge_m_info), \
> + INTEL_IVB_D_IDS(&intel_ivybridge_d_info), \
> + INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), \
> + INTEL_HSW_D_IDS(&intel_haswell_d_info), \
> + INTEL_HSW_M_IDS(&intel_haswell_m_info), \
> + INTEL_VLV_M_IDS(&intel_valleyview_m_info), \
> + INTEL_VLV_D_IDS(&intel_valleyview_d_info)
> +
> static const struct pci_device_id pciidlist[] = { /* aka */
> - INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
> - INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
> - INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */
> - INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
> - INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */
> - INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */
> - INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */
> - INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */
> - INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */
> - INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */
> - INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */
> - INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */
> - INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */
> - INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */
> - INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */
> - INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */
> - INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */
> - INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */
> - INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */
> - INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */
> - INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */
> - INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */
> - INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */
> - INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */
> - INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */
> - INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */
> - INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */
> - INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
> - INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
> - INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
> - INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
> - INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
> - INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
> - INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
> - INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
> - INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
> - INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
> - INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
> - INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
> - INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
> - INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
> - INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
> - INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
> - INTEL_QUANTA_VGA_DEVICE(&intel_ivybridge_q_info), /* Quanta transcode */
> - INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
> - INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
> - INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
> - INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT3 desktop */
> - INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
> - INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
> - INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT3 server */
> - INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
> - INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
> - INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
> - INTEL_VGA_DEVICE(0x040B, &intel_haswell_d_info), /* GT1 reserved */
> - INTEL_VGA_DEVICE(0x041B, &intel_haswell_d_info), /* GT2 reserved */
> - INTEL_VGA_DEVICE(0x042B, &intel_haswell_d_info), /* GT3 reserved */
> - INTEL_VGA_DEVICE(0x040E, &intel_haswell_d_info), /* GT1 reserved */
> - INTEL_VGA_DEVICE(0x041E, &intel_haswell_d_info), /* GT2 reserved */
> - INTEL_VGA_DEVICE(0x042E, &intel_haswell_d_info), /* GT3 reserved */
> - INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
> - INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
> - INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT3 desktop */
> - INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
> - INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
> - INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT3 server */
> - INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
> - INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
> - INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT3 mobile */
> - INTEL_VGA_DEVICE(0x0C0B, &intel_haswell_d_info), /* SDV GT1 reserved */
> - INTEL_VGA_DEVICE(0x0C1B, &intel_haswell_d_info), /* SDV GT2 reserved */
> - INTEL_VGA_DEVICE(0x0C2B, &intel_haswell_d_info), /* SDV GT3 reserved */
> - INTEL_VGA_DEVICE(0x0C0E, &intel_haswell_d_info), /* SDV GT1 reserved */
> - INTEL_VGA_DEVICE(0x0C1E, &intel_haswell_d_info), /* SDV GT2 reserved */
> - INTEL_VGA_DEVICE(0x0C2E, &intel_haswell_d_info), /* SDV GT3 reserved */
> - INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
> - INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
> - INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT3 desktop */
> - INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
> - INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
> - INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT3 server */
> - INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
> - INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
> - INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT3 mobile */
> - INTEL_VGA_DEVICE(0x0A0B, &intel_haswell_d_info), /* ULT GT1 reserved */
> - INTEL_VGA_DEVICE(0x0A1B, &intel_haswell_d_info), /* ULT GT2 reserved */
> - INTEL_VGA_DEVICE(0x0A2B, &intel_haswell_d_info), /* ULT GT3 reserved */
> - INTEL_VGA_DEVICE(0x0A0E, &intel_haswell_m_info), /* ULT GT1 reserved */
> - INTEL_VGA_DEVICE(0x0A1E, &intel_haswell_m_info), /* ULT GT2 reserved */
> - INTEL_VGA_DEVICE(0x0A2E, &intel_haswell_m_info), /* ULT GT3 reserved */
> - INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */
> - INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */
> - INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT3 desktop */
> - INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */
> - INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */
> - INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT3 server */
> - INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */
> - INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */
> - INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT3 mobile */
> - INTEL_VGA_DEVICE(0x0D0B, &intel_haswell_d_info), /* CRW GT1 reserved */
> - INTEL_VGA_DEVICE(0x0D1B, &intel_haswell_d_info), /* CRW GT2 reserved */
> - INTEL_VGA_DEVICE(0x0D2B, &intel_haswell_d_info), /* CRW GT3 reserved */
> - INTEL_VGA_DEVICE(0x0D0E, &intel_haswell_d_info), /* CRW GT1 reserved */
> - INTEL_VGA_DEVICE(0x0D1E, &intel_haswell_d_info), /* CRW GT2 reserved */
> - INTEL_VGA_DEVICE(0x0D2E, &intel_haswell_d_info), /* CRW GT3 reserved */
> - INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
> - INTEL_VGA_DEVICE(0x0f31, &intel_valleyview_m_info),
> - INTEL_VGA_DEVICE(0x0f32, &intel_valleyview_m_info),
> - INTEL_VGA_DEVICE(0x0f33, &intel_valleyview_m_info),
> - INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
> - INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
> + INTEL_PCI_IDS,
> {0, 0, 0}
> };
>
> diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
> index 63d609d..dc480f5 100644
> --- a/include/drm/i915_drm.h
> +++ b/include/drm/i915_drm.h
> @@ -34,4 +34,184 @@ extern bool i915_gpu_raise(void);
> extern bool i915_gpu_lower(void);
> extern bool i915_gpu_busy(void);
> extern bool i915_gpu_turbo_disable(void);
> +
> +#define INTEL_VGA_DEVICE(id, info) { \
> + .class = PCI_BASE_CLASS_DISPLAY << 16, \
> + .class_mask = 0xff0000, \
> + .vendor = 0x8086, \
> + .device = id, \
> + .subvendor = PCI_ANY_ID, \
> + .subdevice = PCI_ANY_ID, \
> + .driver_data = (unsigned long) info }
> +
> +#define INTEL_QUANTA_VGA_DEVICE(info) { \
> + .class = PCI_BASE_CLASS_DISPLAY << 16, \
> + .class_mask = 0xff0000, \
> + .vendor = 0x8086, \
> + .device = 0x16a, \
> + .subvendor = 0x152d, \
> + .subdevice = 0x8990, \
> + .driver_data = (unsigned long) info }
> +
> +#define INTEL_I830_IDS(info) \
> + INTEL_VGA_DEVICE(0x3577, info)
> +
> +#define INTEL_I845G_IDS(info) \
> + INTEL_VGA_DEVICE(0x2562, info)
> +
> +#define INTEL_I85X_IDS(info) \
> + INTEL_VGA_DEVICE(0x3582, info), /* I855_GM */ \
> + INTEL_VGA_DEVICE(0x358e, info)
> +
> +#define INTEL_I865G_IDS(info) \
> + INTEL_VGA_DEVICE(0x2572, info) /* I865_G */
> +
> +#define INTEL_I915G_IDS(info) \
> + INTEL_VGA_DEVICE(0x2582, info), /* I915_G */ \
> + INTEL_VGA_DEVICE(0x258a, info) /* E7221_G */
> +
> +#define INTEL_I915GM_IDS(info) \
> + INTEL_VGA_DEVICE(0x2592, info) /* I915_GM */
> +
> +#define INTEL_I945G_IDS(info) \
> + INTEL_VGA_DEVICE(0x2772, info) /* I945_G */
> +
> +#define INTEL_I945GM_IDS(info) \
> + INTEL_VGA_DEVICE(0x27a2, info), /* I945_GM */ \
> + INTEL_VGA_DEVICE(0x27ae, info) /* I945_GME */
> +
> +#define INTEL_I965G_IDS(info) \
> + INTEL_VGA_DEVICE(0x2972, info), /* I946_GZ */ \
> + INTEL_VGA_DEVICE(0x2982, info), /* G35_G */ \
> + INTEL_VGA_DEVICE(0x2992, info), /* I965_Q */ \
> + INTEL_VGA_DEVICE(0x29a2, info) /* I965_G */
> +
> +#define INTEL_G33_IDS(info) \
> + INTEL_VGA_DEVICE(0x29b2, info), /* Q35_G */ \
> + INTEL_VGA_DEVICE(0x29c2, info), /* G33_G */ \
> + INTEL_VGA_DEVICE(0x29d2, info) /* Q33_G */
> +
> +#define INTEL_I965GM_IDS(info) \
> + INTEL_VGA_DEVICE(0x2a02, info), /* I965_GM */ \
> + INTEL_VGA_DEVICE(0x2a12, info) /* I965_GME */
> +
> +#define INTEL_GM45_IDS(info) \
> + INTEL_VGA_DEVICE(0x2a42, info) /* GM45_G */
> +
> +#define INTEL_G45_IDS(info) \
> + INTEL_VGA_DEVICE(0x2e02, info), /* IGD_E_G */ \
> + INTEL_VGA_DEVICE(0x2e12, info), /* Q45_G */ \
> + INTEL_VGA_DEVICE(0x2e22, info), /* G45_G */ \
> + INTEL_VGA_DEVICE(0x2e32, info), /* G41_G */ \
> + INTEL_VGA_DEVICE(0x2e42, info), /* B43_G */ \
> + INTEL_VGA_DEVICE(0x2e92, info) /* B43_G.1 */
> +
> +#define INTEL_PINEVIEW_IDS(info) \
> + INTEL_VGA_DEVICE(0xa001, info), \
> + INTEL_VGA_DEVICE(0xa011, info)
> +
> +#define INTEL_IRONLAKE_D_IDS(info) \
> + INTEL_VGA_DEVICE(0x0042, info)
> +
> +#define INTEL_IRONLAKE_M_IDS(info) \
> + INTEL_VGA_DEVICE(0x0046, info)
> +
> +#define INTEL_SNB_D_IDS(info) \
> + INTEL_VGA_DEVICE(0x0102, info), \
> + INTEL_VGA_DEVICE(0x0112, info), \
> + INTEL_VGA_DEVICE(0x0122, info), \
> + INTEL_VGA_DEVICE(0x010A, info)
> +
> +#define INTEL_SNB_M_IDS(info) \
> + INTEL_VGA_DEVICE(0x0106, info), \
> + INTEL_VGA_DEVICE(0x0116, info), \
> + INTEL_VGA_DEVICE(0x0126, info)
> +
> +#define INTEL_IVB_M_IDS(info) \
> + INTEL_VGA_DEVICE(0x0156, info), /* GT1 mobile */ \
> + INTEL_VGA_DEVICE(0x0166, info) /* GT2 mobile */
> +
> +#define INTEL_IVB_D_IDS(info) \
> + INTEL_VGA_DEVICE(0x0152, info), /* GT1 desktop */ \
> + INTEL_VGA_DEVICE(0x0162, info), /* GT2 desktop */ \
> + INTEL_VGA_DEVICE(0x015a, info), /* GT1 server */ \
> + INTEL_VGA_DEVICE(0x016a, info) /* GT2 server */
> +
> +#define INTEL_IVB_Q_IDS(info) \
> + INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */
> +
> +#define INTEL_HSW_D_IDS(info) \
> + INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
> + INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
> + INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \
> + INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \
> + INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \
> + INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \
> + INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \
> + INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \
> + INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \
> + INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \
> + INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \
> + INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \
> + INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \
> + INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \
> + INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \
> + INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \
> + INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \
> + INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \
> + INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \
> + INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \
> + INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \
> + INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \
> + INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \
> + INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \
> + INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
> + INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
> + INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
> + INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
> + INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
> + INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
> + INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \
> + INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
> + INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
> + INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \
> + INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \
> + INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \
> + INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \
> + INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \
> + INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \
> + INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \
> + INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \
> + INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \
> + INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \
> + INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \
> + INTEL_VGA_DEVICE(0x0D2E, info) /* CRW GT3 reserved */ \
> +
> +#define INTEL_HSW_M_IDS(info) \
> + INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
> + INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
> + INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \
> + INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
> + INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
> + INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
> + INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
> + INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \
> + INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
> + INTEL_VGA_DEVICE(0x0A0E, info), /* ULT GT1 reserved */ \
> + INTEL_VGA_DEVICE(0x0A1E, info), /* ULT GT2 reserved */ \
> + INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \
> + INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \
> + INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \
> + INTEL_VGA_DEVICE(0x0D26, info) /* CRW GT3 mobile */
> +
> +#define INTEL_VLV_M_IDS(info) \
> + INTEL_VGA_DEVICE(0x0f30, info), \
> + INTEL_VGA_DEVICE(0x0f31, info), \
> + INTEL_VGA_DEVICE(0x0f32, info), \
> + INTEL_VGA_DEVICE(0x0f33, info), \
> + INTEL_VGA_DEVICE(0x0157, info)
> +
> +#define INTEL_VLV_D_IDS(info) \
> + INTEL_VGA_DEVICE(0x0155, info)
> +
> #endif /* _I915_DRM_H_ */
> --
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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