[Intel-gfx] [PATCH 2/2] drm/i915: fix pnv display core clock readout out

[Daniel Vetter]

On Fri, Jul 26, 2013 at 11:18:21AM +0300, Jani Nikula wrote:
> On Fri, 26 Jul 2013, Daniel Vetter <daniel.vetter at ffwll.ch> wrote:
> > We need the correct clock to accurately assess whether we need to
> > enable the double wide pipe mode or not.
> >
> > Cc: Chris Wilson <chris at chris-wilson.co.uk>
> > Cc: Stéphane Marchesin <marcheu at chromium.org>
> > Cc: Stuart Abercrombie <sabercrombie at google.com>
> > Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h      |  6 ++++++
> >  drivers/gpu/drm/i915/intel_display.c | 29 ++++++++++++++++++++++++++++-
> >  2 files changed, 34 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 6caa748..3aebe5d 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -61,6 +61,12 @@
> >  #define   GC_LOW_FREQUENCY_ENABLE	(1 << 7)
> >  #define   GC_DISPLAY_CLOCK_190_200_MHZ	(0 << 4)
> >  #define   GC_DISPLAY_CLOCK_333_MHZ	(4 << 4)
> > +#define   GC_DISPLAY_CLOCK_267_MHZ_PNV	(0 << 4)
> > +#define   GC_DISPLAY_CLOCK_333_MHZ_PNV	(1 << 4)
> > +#define   GC_DISPLAY_CLOCK_444_MHZ_PNV	(2 << 4)
> > +#define   GC_DISPLAY_CLOCK_200_MHZ_PNV	(5 << 4)
> > +#define   GC_DISPLAY_CLOCK_133_MHZ_PNV	(6 << 4)
> > +#define   GC_DISPLAY_CLOCK_167_MHZ_PNV	(7 << 4)
> >  #define   GC_DISPLAY_CLOCK_MASK		(7 << 4)
> >  #define   GM45_GC_RENDER_CLOCK_MASK	(0xf << 0)
> >  #define   GM45_GC_RENDER_CLOCK_266_MHZ	(8 << 0)
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index b3389d7..3e66f05 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -4163,6 +4163,30 @@ static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
> >  	return 200000;
> >  }
> >  
> > +static int pnv_get_display_clock_speed(struct drm_device *dev)
> > +{
> > +	u16 gcfgc = 0;
> > +
> > +	pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
> > +
> > +	switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
> > +	case GC_DISPLAY_CLOCK_267_MHZ_PNV:
> > +		return 267000;
> > +	case GC_DISPLAY_CLOCK_333_MHZ_PNV:
> > +		return 333000;
> > +	case GC_DISPLAY_CLOCK_444_MHZ_PNV:
> > +		return 444000;
> > +	case GC_DISPLAY_CLOCK_200_MHZ_PNV:
> > +		return 200000;
> > +	default:
> > +		DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
> 
> Reading the spec, should the default/fallback be 333 MHz for desktop?
> Otherwise,

As discussed on irc the default case should never happen, but I've simply
picked the slowest frequency to be on the safe side and hopefully show
something on the screen.

> Reviewed-by: Jani Nikula <jani.nikula at intel.com>

Queued for -next, thanks for the review.
-Daniel

> 
> > +	case GC_DISPLAY_CLOCK_133_MHZ_PNV:
> > +		return 133000;
> > +	case GC_DISPLAY_CLOCK_167_MHZ_PNV:
> > +		return 167000;
> > +	}
> > +}
> > +
> >  static int i915gm_get_display_clock_speed(struct drm_device *dev)
> >  {
> >  	u16 gcfgc = 0;
> > @@ -9605,9 +9629,12 @@ static void intel_init_display(struct drm_device *dev)
> >  	else if (IS_I915G(dev))
> >  		dev_priv->display.get_display_clock_speed =
> >  			i915_get_display_clock_speed;
> > -	else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
> > +	else if (IS_I945GM(dev) || IS_845G(dev))
> >  		dev_priv->display.get_display_clock_speed =
> >  			i9xx_misc_get_display_clock_speed;
> > +	else if (IS_PINEVIEW(dev))
> > +		dev_priv->display.get_display_clock_speed =
> > +			pnv_get_display_clock_speed;
> >  	else if (IS_I915GM(dev))
> >  		dev_priv->display.get_display_clock_speed =
> >  			i915gm_get_display_clock_speed;
> > -- 
> > 1.8.3.2
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx at lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Jani Nikula, Intel Open Source Technology Center

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch