[Intel-gfx] [PATCH 2/2] drm/i915: Use Write-Through cacheing for the display plane on Iris

[Kenneth Graunke]

On 07/30/2013 09:58 AM, Chris Wilson wrote:
> Haswell GT3e has the unique feature of supporting Write-Through cacheing
> of objects within the eLLC. The purpose of this is to enable the display
> plane to remain coherent whilst objects lie resident in the eLLC - so
> that we in theory get the best of both worlds, perfect display and fast
> access.
>
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Ben Widawsky <ben at bwidawsk.net>

Awesome.  Thanks a ton for doing this, Chris!

Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>