[Intel-gfx] [PATCH 2/2] drm/i915: Use Write-Through cacheing for the display plane on Iris

[Chris Wilson]

On Tue, Jul 30, 2013 at 09:01:22PM +0300, Ville Syrjälä wrote:
> Hmm, and what about CPU access in general? CPU doesn't know about the
> WT policy, so I'm assuming we'd need to flush after all CPU writes.

Hmm, I had assumed the opposite. I've not yet seen signs of cache dirt.
Certainly GTT access should fine, and CPU reads. It is just those CPU
writes we need to worry about, and now I do indeed worry.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre